Multipurpose computerized television

ABSTRACT

A multipurpose computerized television system generates a plurality of video images in association with a personal computer. A television circuit associates with the personal computer and is within the personal computer chassis for receiving a plurality of television signals and directing the signals to the monitor for the monitor to display. An audio multimedia circuit associates with the personal computer and the television circuit and is also located within the chassis for receiving and processing audio data from the television circuit. The audio multimedia circuit also communicates the audio multimedia data to the personal computer. Control circuitry associated with the television circuit and the personal computer within the chassis controls the operation of the television circuit through the personal computer. The control circuitry comprises a remote control circuit for remotely and independently controlling the television circuit and the personal computer.

This application is a continuation of U.S. patent application Ser. No.08/028,402, filed on Mar. 9, 1993 now abondoned, which is continuationof U.S. patent application Ser. No. 07/691,377, filed on Apr. 25, 1991(now U.S. Pat. No. 5,192,999, issued Mar. 9, 1993).

TECHNICAL FIELD OF THE INVENTION

The present invention relates in general to systems for electronicvisual communication, and more particularly provides a multipurposecomputerized television for generating a plurality of video images inassociation with a personal computer.

BACKGROUND OF THE INVENTION

In recent times, numerous electronic technologies including audio signalprocessing, video signal processing and data processing have become moreavailable to individual users. With more advanced electronictechnologies available to users, new and different needs forentertainment and business applications have arisen.

Two areas in which needs for improved entertainment and businessapplications exist are in generating multimedia presentations andtelecommunications. Multimedia refers to the integration of text, audio,graphics, still image and moving pictures into a single,computer-controlled, multimedia product. It includes the combination ofcomputers, video disk or compact disk players, video monitors, opticalscanners, audio cards, music synthesizers, etc., all linked together bypowerful developmental software. Telecommunications, on the other hand,includes applications for communicating by electronic transmissionsignals from devices such as telephones, radio, and television. A numberof factors, however, have precluded the ability of system designers todevelop systems which can fully utilize and integrate multimedia andtelecommunications applications in a single workstation. These factorsinclude public acceptance, excessive costs, system complexity, andincompatibilities among the various electronic technologies.

One particular area in which significant improvements are being made isin television technology. Today, for the above states reasons, there isno system that takes full advantage of the television signal display andmanipulation capabilities that may be possible by combining a multimediaapplications with telecommunications applications. If a television couldbe combined with a computer, then a user could realize significantincreases in receiving and recording television information, as well asmaking the computer a much more valuable tool for the storage anddisplay of information.

One video workstation described in U.S. Pat. No. 4,864,562 to Murakamiet al. (hereinafter “Murakami”) shows the use of a control system thatcollects multiple asynchronous video, audio, graphic and data signalsand retransmits the signals. While the data transmission system ofMurakami discloses a system for transmitting various types of audio andvideo data, it fails to integrate telecommunications and multimediaabilities in a single workstation easily accessible to a user. Moreover,the Murakami invention does not approach the benefits available to theuser in having a standardized personal computer platform combined with ahigh quality television circuit.

Thus, there is a need for a system that effectively combines a highquality television circuit with a personal computer.

There is a need for a system that combines within a single chassis atelevision circuit with a personal computer for a variety of multimediaapplications.

There is a need for a system that permits computer manipulation oftelevision signals to perform operations heretofore only possible withmore expensive and complex systems.

Moreover, there is a need for a system that provides to the user anenvironment of full multimedia and telecommunications capabilities,especially including the ability to receive, store, and communicatevideo information.

SUMMARY OF THE INVENTION

The present invention, accordingly, provides a multipurpose computerizedtelevision system for generating a plurality of video images inassociation with a personal computer. The system comprises a personalcomputer that includes a personal computer chassis and a monitor. Atelevision circuit associates with the personal computer and is withinthe chassis for receiving a plurality of television signals anddirecting the signals to the monitor for the monitor to display. Themonitor is a video graphics array monitor and the television circuit isdesigned to be compatible with video graphics array monitor circuitry.

An audio multimedia circuit associates with the personal computer andthe television circuit and is also located within the chassis forreceiving and processing audio data from the television circuit. Theaudio multimedia circuit also communicates the audio multimedia data tothe personal computer. The audio multimedia circuit comprises an analogmixing circuit for mixing a plurality of analog audio signals and ananalog-to-digital/digital-to-analog converter in association with theanalog mixing circuit to generate analog output signals and directingthem to the analog mixing circuit. Theanalog-to-digital/digital-to-analog converter also associates with theanalog mixing circuit to receive a plurality of analog audio signals togenerate a plurality of digital output signals.

Control circuitry associated with the television circuit and thepersonal computer within the chassis controls the operation of thetelevision circuit through the personal computer. The control circuitrycomprises a remote control circuit for remotely and independentlycontrolling the television circuit and the personal computer.

A technical advantage of the present invention is that it effectivelycombines a high quality television circuit with a personal computer. Forexample, by combining the television circuit with the personal computer,the present invention permits computer control of not only thetelevision, but also a wide variety of interfacing systems. Inparticular, the interfacing circuitry permits a graphical user interfaceto be displayed at the monitor for control of the television and othercomponents associated with the computer for significantly increased usercontrol flexibility.

Another technical advantage of the present invention is that it combineswithin a single chassis a television circuit with a personal computerfor a variety of multimedia applications. The television circuit mayinterface other telecommunications circuits such as a data/fax/voicemodem circuit for telephonic transmission of television signals. As aresult, the present invention provides the ability to interface othercircuitry for telephone conferencing of a local area network or othercommunications path.

Yet another technical advantage of the present invention is that itallows the user to manipulate television signals to perform operationsheretofore only possible with more expensive and complex systems.

In coordination with other telecommunications circuitry and audiomultimedia circuitry, the present invention provides to the user anenvironment of full multimedia and telecommunications capabilities,especially including the ability to receive, store, and communicatetelevision video information.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention and forfurther advantages thereof, reference is now made to the following briefdescription, taken in conjunction with the accompanying figures, inwhich:

FIG. 1 illustrates a diagrammatic view of the multimedia computing andtelecommunications workstation of the present invention;

FIG. 2 shows a block diagram of data/fax/voice modem circuit of apreferred embodiment of the present invention;

FIG. 3 provides a block diagram of television circuit of a preferredembodiment of the present invention;

FIG. 4 illustrates a block diagram of the circuit that combines theAM/FM tuner circuit and infrared remote control circuit portions of thetelecommunications circuitry of the present invention;

FIG. 5 illustrates a block diagram of an audio multimedia circuitry thatperforms the multimedia functions for the preferred embodiment of thepresent invention;

FIGS. 6 through 12 illustrate detailed schematic diagrams thedata/fax/voice modem circuit that comprises part of thetelecommunications circuitry of the present invention;

FIGS. 13 through 21 provide detailed schematic diagrams of televisioncircuit of the preferred embodiment of the present invention;

FIGS. 22 through 25 are detailed schematic diagrams of the AM/FM tunercircuit and infrared remote control circuits of the preferredembodiment;

FIGS. 26 through 40 provide the detailed schematic diagrams for theaudio multimedia circuit of a preferred embodiment of the presentinvention;

FIG. 41 shows component configurations for the expansion board of thepreferred embodiment that contains the data/fax/voice modem circuit ofthe present invention;

FIG. 42 shows component configurations for the preferred embodiment ofthe television expansion board of the present invention;

FIG. 43 shows component configurations for the AM/FM tuner and infraredremote control expansion board of a preferred embodiment of the presentinvention;

FIG. 44 shows component configurations for the audio multimedia board ofthe workstation of the present invention;

FIG. 45 shows the use of an expansion bracket assembly in conjunctionwith the telecommunications and multimedia circuit boards of thepreferred embodiment of the present invention;

FIG. 46 illustrates the further connection of expansion bracket assemblyinto the host computer chassis of the preferred embodiment;

FIG. 47 shows an isometric view of fully-assembled chassis of thepresent invention;

FIG. 48 shows the reverse panel of chassis to illustrate the compactinput output connections associated with the telecommunications inmultimedia circuits of the present invention; and

FIG. 49 provides a hierarchical chart of the application programs,libraries, and device drivers usable in the preferred embodiment of thepresent invention.

DETAILED DESCRIPTION OF THE INVENTION

The preferred embodiment of the present invention is best understood byreferring to the FIGUREs, like numerals being used for like andcorresponding parts of the various drawings.

FIG. 1 illustrates a diagrammatic view of the multimediatelecommunications workstation 10 of the present invention. Themultimedia telecommunications workstation 10 combines telecommunicationscircuitry 12 and multimedia circuitry 14 in a single chassis 20. Theworkstation 10 makes possible operations integrating telecommunicationscircuitry 12 and multimedia circuitry 14 for a variety of business andentertainment purposes.

The workstation 10 of the present invention represents a significantimprovement in electronic flexibility. It provides synergistic operationof a personal computer with a telecommunications network. Thetelecommunications circuitry 12 not only encompasses voice and faxtelecommunications, but also encompasses the telecommunication of datasignals. This permits the user to log telephone calls as they are beingmade and have the telephone calls linked into personal informationmanager software that may manage the user's business contacts. Moreover,the present invention can record actual conversations that the usermakes over telephone line 22 as well as the time of call and otherrelevant data associated with the call. As a further example,conventional telephone systems have limited capacity for automaticdialing and storing of telephone numbers. By associatingtelecommunication circuitry 12 with host computer 24, the presentinvention significantly increases data storage capability to provide anon-line research capability to access the user's entire client base, forexample, in real-time as a conversation takes place.

Another example of the synergism that the present invention affords isseen in the combination of the multimedia circuitry 14 with hostcomputer 24 and telecommunications circuitry 12 for significantimprovements in data communication to the user. For example, supposethat the user accesses a database stored in memory 42 on the life of themusic composer, Beethoven. For this purpose, host computer 24 maycontain one or more data files that include facts of Beethoven's life,video imagery describing Beethoven and his culture and surroundings, acatalogue of the different pieces he wrote, and digitally recorded filesof his music. By using multimedia circuit 14, the present inventionpermits display of textual files and video imagery to monitor 26 or to aprinter connection and audio files to audio multimedia circuit 18 forthe circuit to play high resolution music from the composer. As aresult, workstation 10 provides a significantly improved platform fordelivering multimedia information to the user.

Yet another example of using workstation 10 of the present invention isthe ability to receive video imagery from television circuit 46 andstore the video image as a data file within memory 42 of host computer24. Once stored as a data file, the video imagery may be communicatedvia telecommunications circuitry 12 or stored on a memory device throughan external port from workstation 10.

One more example of using workstation 10 of the present invention is theability to combine windowed video to monitor screen 26 so that the usermay have a portion of the screen of monitor 26 occupied by a smallwindowed video image from television circuit 46 while at the same timeperforming word processing or receiving textual data at monitor screen26. For applications such as monitoring financial news via a financialnews network, while at the same time working with or receiving otherfinancial data, the present invention can provide significantly improveddata and information delivery to the user.

Referring more particularly to FIG. 1, telecommunications circuitry 12of the present invention provides the user with the ability to send andreceive computer data, facsimile transmissions and voice and audio soundover one or more conventional telephone lines 22. The user also has theability to receive and record radio frequency and television signalsusing workstation 10. The radio and television signals may be recordedwithin workstation 10 and electronically connected to telephone line 22for transmission as audio sound or digital data.

Multimedia circuitry 14 includes visual multimedia circuitry 16 andaudio multimedia circuitry 18. Visual multimedia circuitry 16 includes ahost computer 24 and monitor 26 for use with multimedia computersoftware algorithms to create a variety of visual images and videodisplays. Audio multimedia circuitry 18 includes compact disk read-onlymemory device (CD-ROM) 28, MIDI interface 30 (which actually provides atelecommunications port for multimedia digital sound inputs),analog-to-digital/digital-to-analog converter 32 for manipulatingdigital and analog signals, and sound synthesizer 33 for generatingnumerous synthesized sounds.

Host computer 24, in the preferred embodiment, is an IBM PC-ATcompatible system with a 10 MHz 80286 or similarly equippedmicroprocessor. Host computer 24 may include a math coprocessor, andsupports 1 to 16 MB of expandable random access memory. Input devices toworkstation 10 may include keyboard 34, which in the preferredembodiment has 101 keys, and two button mouse 36.

Workstation chassis 20 is approximately 17″×17″×3.5″ to combine a slim,low-profile look with a minimum footprint. As well as accommodatingCD-ROM 28, chassis 20 may include 5.25″, ½ height, 1.2 MB floppy drive38, 3.5″, ½ height, 1.44 MB floppy drive 40, and 3.5″40 MB hard drive42.

Telecommunications circuitry 12 within workstation 10 includesdata/fax/voice modem circuit 44, television circuit 46, AM/FM tunercircuit 48, and remote control circuit 50. Host computer 24 providesdigital control to all components within telecommunications circuitry12. The user may control operation of host computer 24 fortelecommunication purposes using keyboard 34 or mouse 36. Additionally,the user may communicate with host computer 24 using remote controller52 through remote control circuit 50.

Data/fax/voice modem circuit 44 communicates via telephone line 22 tosend and receive digital data signals 54, fax and voice signals 58 andaudio signals 60. Television circuit 46 may receive video signals frombroadcast television 62, cable television 64, or analog data input 66from a video cassette recorder or video laser disk player. AM/FM tunercircuit 48 provides audio signals 68 to audio multimedia circuitry 18.Audio multimedia circuitry 18 may direct the signals 68 to variouscircuitry within workstation 10. For example, signals may be directedafter digitization by A/D Converter 32 to host computer 24 for storagein memory or to data/fax/voice modem circuit 44 for sending on telephoneline 22.

Host computer 24, operating in conjunction with installed multimediasoftware algorithms and television circuit 46, provides digitalmultimedia output to monitor 26. Monitor 26 generates a video graphicsarray (VGA) display that may encompass a wide assortment of videomultimedia signals. FIG. 49 and associated text describes the variousapplication programs and device drivers that are used in conjunctionwith the output from audio multimedia circuitry 18 of the presentinvention.

Host computer 24 also controls the audio signals of workstation 10 viaaudio multimedia circuitry 18. These signals include digital audiosignals from CD-ROM 28, A/D-D/A converter 32, and sound synthesizer 33.To properly mix these signals, audio multimedia circuitry 18 comprises7:1 mixer 70. 7:1 mixer 70 may also receive input from televisioncircuit 46 and AM/FM tuner circuit 48. An auxiliary input, aux 172 mayreceive analog signals from external inputs, including audio cassette oradditional VCR or television inputs. Audio multimedia circuitry 18 mayalso receive analog microphone signals from microphone input 76. Soundsignals from audio multimedia circuitry 18 may be directed to selectableoutputs such as line level audio 78, variable audio 80, headphone audio82, or handset audio 84.

FIG. 2 shows a block diagram of data/fax/voice modem circuit 44. Hostcomputer bus interface 300 provides data and control signals to digitalsignal processor, RC224AT 102. Also in communication with RC224AT 102for data, address, and control signal transmission are V.22 bis datamodem 104, fax/voice modem 106, read-only memory device ROM 108, andrandom access memory device RAM 110. V.22 bis data modem 104 provideshook control and analog signals to DAA 114. The data modem 104 transmitsan analog signal to the DAA circuitry 114. The data modem 104 receiveanalog signal originates from the DAA 114. DAA 114 outputs ring detectdata via line 144 to RC224AT 102 and outputs analog received signals viaanalog signal line 124.

Fax/voice modem 106 transmits analog signals to DAA 114, receives audiosignals from op amp 118 at audio input connection 120 for voice, andreceives analog signals from DAA 114 for FAX modem. DAA 114 sends analogoutput signals to op amp 119 and the amplified signals go to externalaudio output connection 122. Additionally, speaker analog signal line121 from DAA 114 connects to speaker circuit 116. Speaker circuit 116may also receive speaker control signals from RC224AT 102. Output fromspeaker circuit 116 flows to an on board speaker 117 or optionally tochassis speaker 90 via connector 128, or to external speaker connection127. DAA 114 connects to the tip line 148 and ring line 150 of telephoneline 22.

Host computer bus interface 300 provides a communications path betweendata/fax/voice modem circuit 44 and host computer 24. Consequently, IBMPC-AT compatible Industry Standard Architecture (ISA) interfacespecifications define the technical requirements for host computer businterface 300. The data/fax/voice modem circuit 44 is configured toappear to the host computer 24 as a communications circuit.Data/fax/voice modem circuit 44 may connect to one of the COM1, COM2,COM3 or COM4 ports of host computer 24 as provided in the ISAspecification. Because the preferred embodiment uses COM1 and COM2interfaces for other purposes with host computer 24 motherboard, eitherCOM3 or COM4 are preferably used to connect data/fax/voice modem circuit44.

Digital signal processor RC244AT 102 comprises a DTE (data terminalequipment) side 132 and a DCE (data communications equipment) side 134.DTE side 132 integrates a 16450 compatible interface. The DCE side 134is connected to the IA10464 chip 104. The IA10464 chip 104 convertsdigital signals to analog signals and vice versa. The RC224AT processorincludes an expansion bus 138 that permits connecting, for example,fax/voice modem 106, ROM device 108 and RAM device 110.

In the preferred embodiment, components of the data/fax/voice modemcircuit 44 satisfy various important industry standards. For example,V.22 bis data modem 104 satisfies CCITT requirements, and is compatiblewith V.22 A/B, Bell 212A, Bell 103 and supports the Hayes “AT”2400Bcommand set. Fax/voice modem 106 facsimile portion satisfies the CCITTV.29, V.27 ter, T.30, V.21, T.4 and Group 3 requirements for facsimiletransmit/receive with class I software support. The voice portion offax/voice modem 106 has the ability to perform voice modetransmit/receive with DTMF generation/reception and is connected with an8 kilobyte RAM for data buffering.

The V.22 bis data modem 104 includes necessary circuitry for associatingIA10464 chip 104 with DAA (Data Access Arrangement) interface 114. Otherpertinent details respecting V.22 bis data modem 104 are provided belowin connection with the description of its schematic diagram. V.22 bisdata modem 104 operates in a full duplex mode for the transmission ofdata.

Fax/voice modem 106, in the preferred embodiment, is an R96DFX,manufactured by Rockwell International for both facsimile and voicemodem capabilities. The R96DFX chip supports a CCITT standard T.30 orT.4 type interface, and contains firmware to produce discrete packets ofdigital information. Fax/voice modem 106 transmits this digitalinformation to DAA 114 in a half duplex operation mode.

Receive data on line 124 from DAA 114 is connected to the V.22 bis datamodem 104 and fax/voice modem 106. only one modem receives at a time.When V.22 bis data modem 104 is selected to receive, for example,fax/voice modem 106 sits idle, and vice versa. switching between V.22bis data modem 104 and fax/voice modem 106 may be performed by theoperator through host computer 24 control to data/fax/voice modemcircuit 44. Transmit analog signals come from each modem depending onthe modem that the operator enables.

Fax/voice modem 106 produces digitized data from the voice signals itreceives, and produces audio signals from digital data files. Thispermits a user to play back a recording for transmission acrosstelephone line 22. ROM 108 in data/fax/voice modem circuit 44 storesnecessary data to perform these functions. A portion of ROM 108 is alsoallocated to support necessary memory functions for the fax/voice modem106 interface with the remainder of data/fax/voice modem circuit 44.

The voice data is sampled at a sample frequency of 9600 samples persecond. Because of the amount of data that sampling at 9600 samples persecond generates, data compression is necessary. A compressionalgorithm, ADPCM (i.e., Adaptive Differential Pulse Code Modulation), isused to compress and decompress data for these purposes. Using ADPCMalgorithm reduces the amount of data that needs to be stored or playedback. The ADPCM algorithm can be used to decompress previouslycompressed data for playing a message or to compress data to record amessage. Thus firmware contained in ROM 108 may act with the hostsoftware to move a block of compressed data from memory to generate anoutgoing message and then record an incoming message. This permitsworkstation 10 to act as a telephone answering machine.

Because the ADPCM algorithm compresses a large amount of data, however,it is necessary to temporarily store the uncompressed data. RAM 110holds the uncompressed blocks of data in temporary storage for thispurpose. The data/fax/voice modem circuit 44 circuitry uses part of thenonvolatile memory to store user configurations and phone numbers.

DAA 114 complies with 15 C.F.R. 68, which specifies the electricalcircuitry requirements for interfacing telephone lines. DAA 114 permitsthe data/fax/voice modem circuit 44 connections to telephone line 22 tosatisfy these telephone requirements. In the preferred embodiment, DAA114 is wet transformer-based, requiring a small DC current to activatethe transformer. The DC current is generally taken from telephone line22. The DAA 114 transformer is a 600 Ω-to-600 Ω, 1-to-1 currenttransformer. DAA 114 includes a voltage suppressor circuit, hook controlline 142, and ring detect line 144.

Hook control line 142 and ring detect line 144 are basic to the DAA 114interface. Hook control line 142 generates an on/off hook signal toreport the status of the connection with telephone line 22.

The data/fax/voice modem circuit 44 also contains audio input connection120 and audio output connection 122. These communicate analog signalsbetween other portions of the telecommunications circuitry 12 and theaudio multimedia circuitry 18 and the data/fax/voice modem circuit 44.This permits the user to direct a message that is recorded or beingrecorded from data/fax/modem circuit 44 to audio multimedia circuitry 18for playing on the workstation 10 chassis speaker 90.

As an additional example, the microphone input 76 of audio multimediacircuitry 18 may be switched into the telecommunications circuitry 12through audio input connection 120. This provides an auxiliary input,such as a microphone signal, to go to fax/voice modem 106 and out totelephone line 22. This permits the data/fax/voice modem circuit 44 tojoin with the audio multimedia circuitry 18 to provide the user with ahigh-quality speaker telephone having many functional capabilitiesheretofore not available.

Tip line 148 and ring line 150 provide a telephone line 22 interface forDAA 114. In these two lines, current flows in a closed-loop fortelephone line 22 communications. Receive data line 124 takes the samesignal that may go to the audio output connection 122 and directs it tothe speaker circuit 116. Speaker circuit 116 is controlled by Hayes A/Tcommand set to permit the user to turn the speaker on and select threedifferent volume levels: low, medium and high. The preferred embodimentalso permits the user to plug in an external speaker to the speaker lineat external speaker connection 127.

FIG. 3 provides a block diagram of television circuit 46 of a preferredembodiment of the present invention. Input circuit 174 includes acable-ready TV tuner circuit and an input from an external video source.Input circuit 174 is powered by an independent high voltage circuit 178.Input circuit 174 is connected to decoder 190 and Orion 202 via I²C® bus176. The I²C® bus 174 provides for programmed control of the majorcomponents of television circuit 46. In particular, in the input circuitit provides for channel selection of the tuner circuit. I²C® bus is apatented bus structure owned by Phillips Corporation.

Coming from input circuit 174 are CVBBO and CVBB1 signals 182, TV audiosignal 184 and VCR audio signal 186. The signals on lines 182 for CVBB0and CVBB1 go to decoder 190. Output from decoder 190, includes analogcontrol signal, ANCTL 192, and decoded video signals 194. In addition tosignals 194 of BC, BY and DV from decoder 190, P and FC signals 196,I²C® bus 176, and bus, SA, and LA signals 198 go to Orion 202. FC line200 also connects to processor 222. Also, SD line 204 connects to Orion202.

Orion 202 provides output signals RCON and MA 210 to VRAM 220 and CD andCY signals 208 to VRAM 220. PMCS16/signal 212 feeds from Orion 202 intohost interface 244. Also, PRDY signals 216 from Orion 202 goes to hostinterface 244. Finally, BNDBL and DACL signals from Orion 202 feed toprocessor 222. Video processor 222 outputs include I₂C®, signals toOrion 202 and REDO, GREENO and BLUEO signals 232 to output 226 and DACsignals 223 to audio circuit 224. Output circuit 226 receives REDO,GREENO and BLUEO signals 232, KEYO signals 218, LINEOUT signals 238, andAMPOUT signals 234 and transmits video signals 236 to VGA monitor 26.Audio output circuit 224 receives digital analog control signals 223,TVAUDIO signal 184, analog control signal ACNTL 192 and VCRAUDIO signal186 to generate LINEOUT signal 238 and AMPOUT signal 234, as previouslystated.

Television circuit 46 is an IBM PC-AT compatible single slot add-incircuit that is placed on an add-in card that integrates full motionvideo and audio with personal computer 24. Computer 24 is required tohave a VGA or SVGA graphics card and analog black and white or colormonitor. A user provides a video source like an antenna or VCR to thecard which transforms the incoming video signals onto monitor 26display, mixing the new video with the traditional PC display.

Attributes of the input image such as channel, image size, cropping,color, contrast, volume are varied via the computer through the userinterface programs. TV circuit 46, in addition to providing live video,is a high-resolution true-color still image display and capture card.Vivid still images may be displayed on the video monitor 26, mixed withvideo signals from host computer 24, and saved to a disk for less costthan with known circuitry. This feature makes applications such asteleconferencing over a local area network possible. Television circuit46 provides a user accessibility to live video and high quality stillimages through an easy to use computer interface.

Hardware of television circuit 46 is configured to run under DOS, or agraphical user interface software package, such as Windows 3.0 orMultimedia Windows. Possible uses for television circuit 46 include,video tape training, interactive software with video laser diskconnection, sales kiosk, full speed teleconferencing using dedicatedcabling, and reduced frame rate video phone conferencing over a localarea network. Additionally, uses such as security monitoring, in-officereception of presentations and classes and television news, financialnetwork monitoring, and entertainment are also possible using televisioncircuit 46 in the preferred embodiment of the present invention.

The motion video signal may be of two formats: baseband NTSC and RFmodulated NTSC. In other words, the user may plug in a VCR, camcorder,laser video disk player, antenna, cable TV or any signal compatible withthese. There is also an audio input which would come from a VCR typedevice. Host computer 24 video from a VGA circuit may also be input totelevision circuit 46, as well as internal digital color informationfrom a host computer 24 graphic card. The mixed video is output to ananalog monitor, such as VGA monitor 26. In the preferred invention,audio is fed through audio multimedia circuit 18 and output to chassisspeakers. Television circuit 46 may also be used independently with anonboard amplifier that outputs to a speaker. Digital still image datamay be loaded into television circuit 46 from host computer 24. Thisdata may be a picture from a multimedia application and may come from anelectronic mail or local area network.

Also, in association with television circuit 46 of the present inventionmay be circuitry for full speed teleconferencing of telephone signalsand video images using a dedicated cable network. A video telephonecircuit may also be supported using the combination of televisioncircuit 46 and data/fax/voice modem circuit 44 over a local areanetwork.

FIG. 4 illustrates a block diagram of the circuit that combines theAM/FM tuner circuit 48 and infrared remote control circuit 50 portionsof the telecommunications circuitry of the present invention.

For receipt of AM/FM radio transmissions, FM antennae 250 and AMantennae 266 mount to chassis 20 and connect to antennae connections 252and 268, respectively. Antennae connections 252 and 268 provide radiofrequency signals to AM/FM tuner 256. PLL frequency synthesizer 254receives frequency input commands from 8742 programmable 8-bit processor262 and controls the tuning of AM/FM tuner 256.

AM/FM tuner 256 sends audio data to audio bus connection 258 via analogswitch 270. Analog switch also receives control signals from 8742processor 262 and provides line level audio to multimedia audioconnector and volume circuit 272. Volume circuit 272 also receives 126bus signals and control signals from 8742 processor 262. Outputs fromvolume circuit 272 go to power amp 274. Power amp 274 drives speaker outconnection 278. Line out connection 276 goes to head phones 330. Speakerout 278 signals go to speakers 280 and 284. Also communicating with 8742processor 262 is remote control circuit 50. The 8742 processor 262interfaces host computer 24 at host bus 300 for control and datatransmission.

AM/FM tuner circuit 48 includes AM/FM tuner 256 capable of both presetand manual tuning. Seek and scan functions may be programmed into AM/FMtuner 256 for AM and FM channel selection. AM/FM tuner 256 provides areadable lock signal once a frequency is detected and reports thisinformation to 8742 programmable 8-bit processor 262.

The AM/FM tuner 256 consists of the AM and FM sections that arecontrolled by external tuning voltages. Selection of AM or FM activatesan appropriate tuning voltage, FMVCC or AMVCC, and the off switchdisables both Vcc supplies. In the preferred embodiment, AM/FM tuner 256is a TFTCI tuner module manufactured by ALPs. AM/FM tuner PLL frequencysynthesizer 254 generates a tuning voltage for a given station (AM orFM) based on the phase difference between the PLL reference frequencyand AM/FM tuner 256 frequency. This tuning. voltage difference controlsthe AM/FM tuner 256 frequency. When the PLL frequency synthesizer 254and AM/FM tuner 256 are in phase, the tuning voltage remains at a fixedlevel and the tuner is “locked.” When the PLL synthesizer 254 and localoscillator in tuner 256 are not in phase, tuning voltage is adjusted tochange the AM/FM tuner 256 frequency and bring the AM/FM tuner 256 backinto a “locked” condition. Based on control signals from 8742programmable 8-bit processor 262, host computer 24 loads PLL frequencysynthesizer 254 with the frequency to which it must lock.

Remote control circuit 50 for workstation 10 utilizes infrared signaltransmission to permit device and channel selection. Device selectionmay include, for example, television circuit 46, AM/FM tuner circuit 48,CD-ROM 28 from audio multimedia circuitry or data/fax/voice modemcircuit 44 and telephone line 22. Remote control circuit 50 may alsocontrol the MIDI 30 of telecommunications circuitry 12 and permit theuser to program answering machine functions through data/fax/voice modemcircuit 44. Additionally, remote volume control of various sound sourcesfrom workstation 10 is possible using the remote control device. Channelselection may also occur within a particular device selection, such aschannels for television, radio channels, or compact disk channels.

During operation, the 8742 programmable 8-bit processor 262 controlshost interface 300 for remote control functions as well as for AM/FMfrequency tuning functions explained above. The 8742 programmable 8-bitprocessor 262 constantly samples the infrared detector for unique codedvalues that control operation of the interface. The 8742 maintains a64-byte FIFO for multiple keystrokes and interrupts the host computer 24for servicing.

FIG. 5 illustrates a block diagram of an audio multimedia circuitry thatperforms the multimedia functions for the preferred embodiment of thepresent invention. Multimedia facilities available to the user includean audio CD player, an audio control center, a digital audio recorder, amusic synthesizer, and on-board analog audio mixing capabilities. Theaudio multimedia portion of the multimedia communications workstationcomprises a CD-ROM and the audio multimedia board.

Referring to FIG. 5, the block diagram illustrates the connection ofhost computer 24 interface 300 between internal connections 302 andexternal connections 304. Internal connections include a connection 344from the audio portion of television circuit 46, connection 306 fromAM/FM tuner circuit 48 and telephone connections 308 and 309 fromData/Fax/Modem 44. These connect directly to 7:1 mixer 70. SCSIinterface 310 communicates through SCSI internal connection 317. MIDIinterface connector 314 provides an external communication path viaexternal connections 304 to Musical Instrument Digital Interface (MIDI)30.

Along with inputs from AM/FM tuner circuit 48 and Data/Fax/Modem 44, 7:1mixer 70 receives inputs from sound synthesizer 33, A/D-D/A converter32, CD-ROM 28, aux input 72, TV Tuner 46 and serial bus controller 316.Output from 7:1 mixer 70 goes to volume/tone control circuit 318, whichalso receives direct input from serial bus controller 316. Volume/tonecontroller 318 inputs to line out connection 320 for headset connection330 via switch 324. Alternatively, from switch 324 volume/tone controloutput goes to power amplifier 326. Speaker output 328 receives outputand transmits speaker signals to external speakers 125 and 126 orinternal chassis speaker 90 via connector 336.

A/D-D/A converter 32 receives input through microphone input 76 and viamicrophone interface 77 from microphone 332, or mixer 70, as well asinput from host computer interface 300.

Sound synthesizer 33 for audio multimedia circuitry 18 providesrealistic sound from workstation 10. The preferred embodiment of theaudio multimedia circuitry 18 uses as sound synthesizer 33 a YamahaYM3812 device that may operate in three voicing modes. The first modecomprises a nine sound simultaneous voicing mode; the second modeutilizes six melodies and five rhythm sound voicing modes. The fiverhythm sound voicing modes include a bass drum, a snare drum, a tom-tom,a top symbol and a high-hat symbol. The third voicing mode utilizes acomposite sine wave speech synthesis mode. Sound synthesizer 33 alsocomprises a built-in low frequency oscillator for vibrato and AMeffects. Sound synthesizer 33 utilizes software that is compatible withAdLib® and Sound Blaster® hardware.

The 8-bit D/A-A/D converter 32 performs linear PCM sampling. Samplerates from 1 kHz to 48 kHz are available for DMA or programmed I/O datatransfer. An interrupt is provided for buffer management. DMA statemachine 315 runs the data handling for A/D-D/A converter 32. It providessynchronized data transfer capabilities without processor intervention.Analog input to A/D-D/A converter 32 is connected from microphone input76 or mixer 70. Microphone input 76 mounts on the rear panel of thechassis to allow audible interaction between the user and audiomultimedia circuitry 18. Microphone input 76 may also interface oneinput of audio switch 334 through voltage controlled amplifier 336.

The SCSI interface 310 provides DMA transfer of 8-bits and PIO transferof 16-bits with interrupts to control the CD-ROM 28. Data transfer rateswith the SCSI interface 310 are up to 4 MBs per second. SCSI interface310 includes a 128-byte FIFO and a SCSI bus with an 8-byte FIFO. In thepreferred embodiment of the present invention, the SCSI interfaceutilizes a controller manufactured by Adaptec, known as the AdaptecAIC-6260 SCSI controller. This is a second generation SCSI controllerwith automatic selection and reselection of SCSI sequences which areperformed by hardware to reduce the host processor intervention duringSCSI device activity. The SCSI controller for CD-ROM use, etc. includesa connector for an external SCSI device and a header for a CD-ROM. TheSCSI interface of the preferred embodiment may support up to seven SCSIdevices, including asynchronous and synchronous SCSI devices. TheAdaptec AIC 6260 SCSI controller utilizes software available fromAdaptec for DOS, OS/2 and UNIX environments and software drivers.

The CD-ROM 28 at internal connection bus 302 and mounted on chassis 20,is capable of sustaining full-bandwidth data transfer from the CD-ROM tomain memory of the host processor. The CD-ROM drive of the multimediaprocessing circuitry of the present invention includes a controllercircuit and cabling. The CD-ROM drive includes a 64 K buffer, with a 1second seek time, capable of sustained 150 KB/second data transfer rateand is made reliable to a level of 10,000 hours mean time betweenfailures.

Musical Instrument Digital Interface (MIDI) 30 may associate withvarious musical instruments capable of generating electronic signals.The MIDI interface comprises three connectors: a MIDI-in, a MIDI-out,and a MIDI-through connector. The device contains integral FIFO,128-byte receive and 16-byte transmit capability, and includestimer/counters for MIDI interface operations. Software to support theMIDI 30 is available through many sources including Voyetra Technologiesof Pelham, N.Y.

The MIDI in/out/through port connection 314 of audio multimediacircuitry 18 allows connection to external MIDI devices and offers asimple interconnection with other workstations for a variety ofpurposes, including synchronization or telecommunication.

The multimedia functions of the present invention use the MultimediaWindows® operator interface program to provide support for digital audioand synthesized music, and other multimedia functions. The MultimediaWindows software has support for 256 color, high resolution images on astandard VGA display.

Audio multimedia circuitry 18 also permits stereo auxiliary input foruser convenience through aux 172. This permits the user to integrateother audio sources as an element of a multimedia presentation. Suchsources may include another CD player, a cassette player, a VCR or videodisk.

Analog mixing control for audio multimedia circuitry 18 is provided by7:1 mixer 70. The 7:1 mixer 70 supports up to 7 analog input signals andallows selection for a combination of inputs. The inputs may includestereo input from CD-ROM 28, monaural input from an A/D-D/A converter32, monaural input from a sound synthesizer 33, stereo input from AM/FMtuner circuit 48, monaural audio input from television circuit 46,stereo input from aux 172 connection, and monaural input from telephoneline 22 via data/fax/voice modem circuit 44. Serial bus controller 316controls the 7:1 mixer 70 in connecting the various inputs it receives.

Master volume/tone control 318 has selectable controls operable throughsoftware, i.e. adjustable volume, bass and treble levels andline/headphone fader control. Switch 324 includes buffered amplifiersfor buffering the line output. Audio power amplifier 326 provides up to2 watts/channel.

FIGS. 6 through 12 illustrate schematic diagrams of significantcomponents of data/fax/voice modem circuit 44 that comprise part of thetelecommunications circuitry 12 of the present invention. In particular,FIG. 6 shows the host computer bus interface 300 and provides the signaldefinitions necessary for the data/fax/voice modem circuit 44 tointerface with the ISA-type host computer 24 bus. Data and controlregisters and bit assignments for the modem circuit 44 are compatiblewith the industry standard 16450 UART.

FIG. 7 illustrates how address selection and interrupt selection is madeby a dip switch 402. Table 1 shows how to select the communication portsCOM1, COM2, COM3 and COM4 to interface data/fax/voice modem circuit 44.

Data buffer 404 buffers the data lines from the host computer 24 bus,and decode circuit 406 decodes the address information.

The RC224AT/2 102 is the primary bus interface for data/fax/voice modemcircuit 44. RC224AT/2 102 connects to the ISA-type host computer 24 businterface 300. From the RC224AT/2 processor lines MI 9 through 1communicate control signals. Address lines include A [15:0] and datalines include lines AD [7:0]. Speaker control signals come from lines430 to the speaker external connection 127. For example, the speakerinterface portion of RC224AT/2 102 includes a number of internalregisters for determining whether or not to turn speaker on or off whenthe data/fax/voice modem circuit 44 is energized.

If the user desires to have the recording portion of data/fax/voicemodem circuit 44 active or not active, the user can store thisconfiguration. There are several different types of commands which canbe set to preload configurations when workstation 10 is initially turnedon. The configuration is determined by the user.

The expansion bus 138 address bus and expansion bus data bus lead fromRC224AT/2 102. The expansion data bus is multiplexed with the addresslines to save pins. A cycle takes place for reading the address and databits from expansion bus 138. On the first part of the cycle, addressbits are latched to extract address information. On the second part ofthe cycle, data bits are sampled for data.

Expansion bus interface 138 for communicating address and data bits fromRC224AT/2 102 is shown in FIG. 8. Referring to the address lines A[15:0] 408 and data lines AD [7:0] 410, expansion bus interface 138includes a 74LS373 434 which latches the address at the first part ofthe cycle. After this occurs, the data lines AD [7:0] are now free totransfer data.

The expansion bus interface PAL 436 decodes the address ranges for ROM108 accesses, RAM 110 accesses, or fax/voice modem 106 accesses.

FIG. 9 illustrates data modem 104 which comprises IA10464 chip 412 forintegrated analog functions to support the MI [9:1] lines coming fromthe RC224AT. The IA10464 chip 412 has D/A converters and A/D convertersto generate DTMF tones for the data modem in a modulation sequence tosupport CCITT V.22 BIS standards. The necessary hardware and code forthese functions are embedded in IA10464 chip 412.

The IA10464 chip 412 includes transmit data line, XMTDATA 414, off-hookcontrol line, OHDATA 416 and talk data control line TLKDATA 418. TheOHDATA 416 indicates whether or not telephone line 22 is connected tothe modems. The TLKDATA 418 indicates whether an external telephone isswitched in or out. Normally, most users will use only one telephoneline 22. The IA10464 chip 418 permits the user to connect telephone line22 so that when data modem 104 and fax/voice modem 106 are not in use,the telephone signal passes through the circuit. This permits thetelephone line 22 to operate as a normal telephone line. On the otherhand, when using the modem capabilities of data/fax/voice modem circuit44, either data modem 104 or fax/voice modem 106 takes over to switchout the phone. Therefore, if data modem 104 or fax/voice modem 106operations take place in workstation 10, the telephone line 22 cannot beused for telephone conversations.

FIG. 10 shows a schematic diagram for fax/voice modem 106 whichcomprises R96DFX chip 438. It includes a data line interface 410 fordata bits AD [7:0], address line 408 for address bits A [4:0], and readand write and chip select lines 472. Other control lines associated withthe R96DFX fax/voice modem 106 include interrupts and reset lines 474.The R96DFX chip 438 has on board analog-to-digital and digital-to-analogconverters for use with the fax and voice portions of the circuit.Outputs from R96DFX 438 include fax/voice transmission line, XMTFAX 478,and EYEX, EYEY, EYECLK, and EYESYNC lines 480. Fax/voice receive line482 and AUXIN line 476 provide input paths to R96DFX chip 438. R96DFX438 provides the capability of transmitting data out. as well asreceiving data on telephone line 22. R96DFX fax/voice modem ismanufactured by Rockwell International of Newport Beach, Calif. andadheres to CCITT V.29 specifications.

FIG. 11 is a schematic view of the DAA 114. DAA 114 includes hookcontrol line 142 and ring detect line 144. Hook control line 142activates two relays to switch the phone lines tip and ring into thecircuit. Ring detector 428 sits across tip and ring lines 148 and 150 tomonitor an incoming ring. The performance level that data/fax/voicemodem circuit 44 must satisfy with respect to the tip and ring lines 148and 150 is specified in 15 CFR Part 68. DAA 114 causes data/fax/voicemodem circuit 44 to satisfy these requirements.

The TLKDATA signal 420 comes from the IA10464 and the talk data relay422 activates the phone relay to allow use of standard telephone forconversations. The transmit data line 414 for the fax/voice modem 106and V.22 bis data modem 104 goes through a summing op amp 424 to asingle point and then goes directly into transformer 426. Transformer426 is part of DAA 114 and takes a DC signal from telephone line 22.Receiver 425 samples the phone data line 429 and subtracts the transmitsignals to derive receive data. The received data, RXA 124 is sent outto fax/voice modem and data modem. At the same time, RXA 124 is sent tothe speaker circuits 446.

FIG. 12 is a diagram of the speaker circuit 116 and shows the flow ofreceive signals labeled RXA from line 124. Using an MC14053 analogswitch 440, the data/fax/voice modem circuit 44 selects the right levelat which to activate output circuit 446 for sending output signals tothe onboard speaker 117. Truth table 442 of FIG. 12 illustrates how toenable the speaker and the levels that appear upon its enabling. Alsoexternal connection 127 permits the connection of an external speaker.The external speaker that may be at connection 127 may be controlledjust as internal speaker 117.

Optional Jumper 128 permits connection to internal chassis speaker 90.

Receive signal RXA on line 124 gets buffered to a line out signal levelto audio multimedia circuitry 18 at 119.

Buffered RXA receive signals go through jack interface circuit 484. Onone side of jack interface is an audio output connection 122, and on theother side is an audio input connection 120. Buffering received signal120 by op amp 118 allows the receipt of audio signals from audiomultimedia circuitry 18 into data/fax/voice modem circuit 44 forultimate output on telephone line 22.

Power requirements for the data/fax/voice modem circuit 44 include +5volts at 500 milliamps, +12 volts at 20 milliamps, and −12 volts at 80milliamps.

FIGS. 13 through 21 detail the schematic diagrams of the majorcomponents of the television circuit.

FIG. 13 provides a detailed schematic diagram of television circuit 46input circuitry 174. Input circuit 174 detailed schematic shows how linelevel video and audio enter a television circuit 46. Tuner module 774 isa cable tuner module which converts cable or broadcast television tobaseband NTSC video. Connector J3 776 allows direct NTSC input from theVCR. Input circuit 174 conditions and filters video signals.

FIG. 14 is a schematic diagram of the TV card decoder section of thetelevision circuitry 46 of a preferred embodiment of the presentinvention. Beginning at analog-to-digital converter 700, which is a TDA8708, this device creates digital signals from analog inputs CVBBO 712and CVBB1 714. Filter circuit 716 provides an antialias filter to filterunwanted noise out of the analog path and decouples components to keeptheir signal levels correct. In the analog-to-digital conversion, it isimportant to keep digital signals away from the analog signals. Thedigital signals are typically of much greater intensity and may corruptthe analog signals. Therefore, it is necessary to separate the groundsand power of the digital noise from the analog input signals. To achievethis, the combination of filter circuit 716 together with ferrite beads,capacitors, and inductors in the power supply nets of digitalmulti-standard decoder (DMSD) 702 and 8-bit A/D converter 700 provideisolation of the devices. The 8-bit A/D converter 700 examines certainportions of the analog wave form to perform automatic gain control andblanking. The signals that DMSD 702 communicates to 8-bit A/D converter700 are digital reference signals that help the converter keepsynchronous with DMSD 702.

Data bits D0-D7 of 8-bit A/D converter 700 provide gain controlled orlevel adjusted representations in the digital domain of the analogsignals coming in the analog side. There is a simple one-to-onecorrespondence between the analog and digital domains. Other connectionsfrom A/D converter 700 include various control signals, including ACNTLfor input source selection and connections to DMSD 702 signals HSY andHC for synchronization control.

The signal between 8-bit A-D converter 700 and DMSD 702, selects thevideo and audio inputs from one source or another. MCLKA/MCLK signalsprovide a common clock signal between DMSD 702 and 8-bit A-D converter700 as generated by SSA9057 704. PAL/NTSC decoder 190, which includesDMSD 702 and SSA9057 704, provides digital television capability thatcan be seen through VGA monitor 26.

DMSD 702 includes a variety of inputs and outputs. These inputs andoutputs include VDD for power in the digital component and VSS for thedigital ground. LL3 provides a clock input and RESET input permits thedigital components to reset upon being powered up. The clock generatorSAA9057 704 provides a reset signal and feeds that signal to DMSD 702.UV0-UV3 generate time multiplexed color difference signals comprising 4bits of UV intensity data. Data bits D1-D7 provide intensityinformation.

Along the bottom of the schematic for DMSD 702 appears HSY connectionfor the horizontal synchronization control signal that tells 8-bit A/Dconverter 700 when blanking or other events are occurring inside thehorizontal line so the analog-to-digital converter knows where it is inthe digital transmission cycle. The VS and BLN bits provide verticalsynchronizing and horizontal synchronizing signals as decoded by DMSD702. XTL1 and XTAL make an oscillator circuit with crystal X1. Line LFCOprovides analog output from the DMSD 702 comprising a signal that keepsthe SAA 9057 704 in synchronous operation with the input video data.Signal bits SDA and SCL provide serial data and clock respectively fromI²C® bus 176 for program input to DMSD 702. BLN provides blankingsignals to line 194. Line IICSA controls internal address selection forthe serial bus.

FIG. 15 provides a schematic diagram of the Orion chip used inconjunction with the television circuit 46. Orion chip 202 is connectedaccording to its application notes and provides scaling, windowing andother features of the television circuitry of the present invention. Itserves as a memory manager, a bus interface and operates as a pixelprocessor to implement windowing and scaling.

Although much of a Orion 202 connectivity is mandated by itsfunctionality, the present invention further includes PAL 16R4 740 whichpermits the use of a “Super VGA” circuit. PAL 16R4 740 takes onefeedback signal and allows pixel-by-pixel control of the output video inany mode. “Super VGA” mode allows a video resolution of 800 pixelshorizontal by 600 pixels vertical, whereas standard VGA resolution is640 pixels by 480 pixels. 74ALS245 chips 742 and 744 further supportthis “Super VGA” mode.

The Orion chip can be programmed by several algorithms to direct outputblock 226 (FIG. 18) to switch video sources. This switching occurs inreal time and results in “picture-in-a-picture” or overlayed videooutput. Functional connections numbered 716 through 734 as illustratedon FIG. 15 are described in the application notes for the Orion part.

Orion 202 from the Chips and Technologies Corporation provides an AT businterface, handles the digital Y:U:V video stream from DMSD 702 andmanages video memory and output switching. Picture size reduction andcropping are achieved through memory management. PAL 16L8 710 and 16R4740 are added with Orion chip 202. The PAL 16L8 fixes known bugs in theOrion 202 circuit. PAL 16R4 740 implements higher-than-standardresolution modes for television circuit 46.

FIG. 16 shows the schematic diagram for VRAM circuit 220. VRAM circuit220 temporarily stores digitized video information. As a result, VRAMcircuit 220 permits frame grabbing by temporarily storing a whole frameof video information. VRAM circuit 220 operates with Orion circuit 202and permits operations such as pixel selection and window reduction viabit manipulation.

FIG. 17 provides a detailed schematic diagram of a digital-to-analogconverter 746 and video processor 206 of a preferred embodiment of thepresent invention. Digital-to-analog converter 746 and video processor206, manufactured by Phillips, convert the digital video from VRAMcircuit 220 into Y:U:V analog data. In association with D/A converter746 is “1-shot” chip 74LS123 748. The “1-shot” chip 748 is a recommendedpart to be used with Orion 202 and provides a pulse in response to areceived signal from the Orion. Output from “1-shot” 748 goes to videoprocessor 206 as an analog step voltage signal. This provides asandcastle signal for use in recreating an analog signal from thedigitized input. Video processor 206 is the Phillips part TDA4680 alongwith pull down resistor and capacitor circuitry 750. Pull down resistorand capacitor circuitry 750 is added to increase the brightness fromvideo processor 206.

FIG. 18 provides a schematic diagram of output circuit 226. Outputcircuit 226 receives red, green and blue 232 and key signals 218 fromvideo processor 206 at multiplexer 752, which in the preferredembodiment is chip 74HCT4053. Multiplexer 752 receives video input 232from video processor 206 and PC video input from an external VGA circuitvia connector 524. Key signal 218 controls whether multiplexer 252 willdirect television or computer output to output connector 592. Op ampcircuit 754 operates as a current mode amplifier that serves as a videobuffer to condition the signal and give it more drive. The video outgoes to monitor 26. Filter circuit 758 connects to an unused video inputassociated with video processor 206. Circuit 758 permits a third videoinput instead of only television input and VCR input.

Line out signal 238 is provided for output to audio multimedia circuitry18 via connector 240, and amp out 238 provides an external speakerconnection via connector 528.

FIG. 19 shows the audio output circuit 224 of the television circuit 46of the present invention. Audio circuit 224 provides for variableamplified control and amplified output within television circuit 46.Audio output circuit 224 is unique in design in that while moreexpensive parts may be available, audio output circuit 224 provides asimple and space economical solution for television audio output.

The personal computer host interface circuit 300 detailed schematic isprovided at FIG. 20. The combination of switch 760 and chip 74LS682 768allows selection of an address range for television circuit 46 andpermits full operation of the Orion chip 202 according to itsapplication notes. The 74LS682 permits allocating different portions ofmemory so that contention with other cards in host computer 24 does notexist.

Feature connector 766 provides access to timing signals that go tomonitor 26, including digital information about colors. Featureconnector 766 permits connecting Orion chip 202 with the VGA controllerin host computer 24. It permits Orion 202 to know which colors are onthe VGA screen. This permits video switching on a color-keyed basis. Forexample, any time the color red is output by the VGA controller, thiscan be detected by Orion 202 and the video output can be switched fromthe controller output to the television output. If the red areaconstituted a circle, then a circular window of television picture wouldappear on the screen in place of the red.

FIG. 21 provides a detailed schematic of power circuit 178 associatedwith television circuit 46. Of particular importance in power circuit178 is diode and oscillator network 770. This provides a boosted voltagefor regulation through zener diode BZX84-C33. This gives a voltage levelthat is not standard for personal computers and that is needed for inputcircuit 74. By generating the necessary output of 30.5 volts at 0 to 3milliamps on board, the power circuit permits use of television circuit46 in a wide variety of personal computer systems.

LM555 is a simple oscillator that is unique in that it uses feedbackfrom a regulator circuit to control the oscillator frequency. Adjustingthe oscillator frequency controls the output voltage, keeping it withina desired range.

Power circuit 178 is designed to minimize EMI radiation and video noisethat degrades picture quality. High voltage circuit 770 uses very fewcomponents and generates little noise at little cost.

FIGS. 22 through 25 illustrate the schematics for the AM/FM tunercircuit and infrared remote control circuit. FIG. 22 provides a detailedschematic diagram of the circuitry associated with the 8742microcontroller 262 in the preferred embodiment of the AM/FM tunercircuit 48 of the present invention. At the upper left hand corner ofFIG. 22 appears a 74F74 flip flop 464 which is designated U508 and whichserves to divide oscillator clock input from AT bus 300 by two. Thistiming signal is fed into the 8742 microcontroller 262. The 8742microcontroller operates as an interface between AT bus 300 and thetuner 48 and remote control 50 functions. 74LS245 271 is a buffer forthe host bus interface 300 on data lines SD [7:0]. All commands gothrough buffer 27 and then to 8742 microcontroller 262. PAL 275 willenable and pass an interrupt. User selection of a system interrupt isprovided by jumper 290. At terminal J3 292 the interrupt can also bepassed over to audio multimedia circuitry 18. This circuit providesinterrupt sharing with circuitry on the multimedia board as part of thepresent invention and would not use interrupt select 290.

Connector J9 294 provides for external connection of an aftermarketinfrared detect circuit. The present invention, however, provides aconnection for internal infrared detect circuit via jumper J8, 280.

PAL 286 serves to decode address information associated with AM/FM tunercircuit 48 and infrared remote control circuit 50.

The AM/FM tuner 48 and infrared remote control circuit 50 are controlledby 8742 programmable 8-bit processor 262. AT bus interface 264 uses acommand and data register protocol to access the 8742 processor 262. Thehex address map for the AM/FM and infrared control board is listed forreference in the following table. The primary address is listed firstand the alternate is listed in parentheses. The board address is jumperselectable.

TABLE 1 I/O Address Cycle Type Register Description 0240 (0250)Read/Write AM/FM/IR data register 0241 (0251) Write only AM/FM/IRcommand register

An interrupt line, IRINT, is sent to the audio multimedia circuit atconnector 292. A logic “1” in either of the two LSBs of an 8-bitinterrupt status register indicates whether the infrared detector orAM/FM tuner need servicing.

The commands for the AM/FM tuner and infrared remote control devices arelisted below for reference. The table contains 8-bit command values forthe 8742 controller 262. The host interface 300 issues the code as anI/O write to the command register and then performs the action forcompleting the command code, i.e., read or write to the AM/FM/IR dataregister.

TABLE 2 Code Function Host Action FF Reset & initialize all N/A externalhardware, i.e. AM/FM tuner & IR remote controller FE Reset & initializeAM/FM tuner N/A only FD Reset IR remote controller N/A FC InterruptStatus Register Read Data FB thru OF not assigned — EF Off/On, AM/FMtuner N/A EE Write AM or FM band select Write Data ED Read AM or FM bandselect Read Data EC Read station lock status Read Data EB Write stationmultiplier Write Data EA Read station multiplier Read Data E9 Stationscan up Write Data E8 Station scan down Write Data E7 AM/FM interruptacknowledge Write E6 thru EO not assigned — DF Valid IR code detected,i.e. Read Data status bit and bytes currently in FIFO DE Read valid IRcommand code, Read Data read data out of FIFO DD IR interruptacknowledge Write DC thru DO not assigned —

FIG. 23 provides a detailed schematic diagram of circuitry associatedwith phase-lock-loop 254. Chip LM317 288 is a voltage regulator whichbrings in 12 volts and generates 8.2 volts for the phase-lock-loop 254circuitry in the AM/FM tuner 256. Phase-lock-loop 254 provides forcontrol selection of AM and FM radio stations. Phase-lock-loop 254responds to input radio frequencies and generates a plurality of outputsthat directly connect to the AM/FM tuner. In the preferred embodiment,phase-lock-loop 254 is part number TSA6057T.

Phase-lock-loop frequency synthesizer 254 generates a tuning voltage fora given station (AM or FM) based on the phase difference between thephase-lock-loop reference frequency and the tuner module 256 localoscillator frequency. This tuning voltage controls the tuner module 256local oscillator frequency. When the phase-lock-loop 254 and AM/FM tuner256 are in phase, the tuning voltage remains at a fixed level and tuner256 is “locked.” When phase-lock-loop 254 and the AM/FM tuner 256 localoscillator are not in phase, the tuning voltage is adjusted to changethe local oscillator frequency and bring tuner 256 back into a “locked”condition.

FIG. 24 provides a detailed schematic drawing of circuitry associatedwith AM/FM tuner 256. AM/FM tuner 256 receives AM antenna input via AMantenna 268 and FM antenna input via antenna 252. The AM antenna 266 andFM antenna 250 are connected to the tuner 256 via a twin coax connector296. AM/FM tuner 256 generates two outputs comprising audio levels leftand right. These outputs go through analog switch 270 which goes eitherto audio multimedia circuitry 18 via J1 448 or to volume control circuit272. Circuitry 259 provides additional control for the selection of AMor FM receive and turns on the power to the AM or FM side of the tunercircuit 256.

AM/FM tuner module 256 contains two tuners whose local oscillators arecontrolled by an external tuning voltage generated by PLL 254. The ONsignal 249 enables or disables the power supply to the selected tuner.AM signal 247 selects which tuning section, AM or FM, will be poweredand enables/disables the appropriate audio outputs from the tuner 256via analog switch 270. The selected audio output then goes to themultimedia circuitry 18 and the volume control 272.

When a station is tuned in and the PLL has “locked” onto the station'sfrequency an interrupt can be generated, either directly via jumper 290or through the multimedia circuitry 18 via connector 292. This can beused to inform the host computer 24 that further action may be required,such as volume unmuting or station display update.

FIG. 25 illustrates the circuitry associated with controller TDA8421 272which provides a speaker volume control, and treble and bass controlsfor the amplified speaker output 278. TDA8421 controller 272 iscontrolled by 8742 262 to select the volume level and the speaker outputand line out signals from AM/FM tuner circuit 48. TDA8421 controller 272controls the signal level at line out connection 276. This output can beconnected to an external amplifier or recording device. Power amplifier,TDA1519AU 274 takes the output signal from TDA 8421 controller 272 andamplifies it to drive two speakers that connect at jack 278.

FIGS. 26 through 40 provide detailed schematic diagrams for thecombination of audio multimedia 18 and certain relatedtelecommunications circuitry 12 of a preferred embodiment of the presentinvention. Specifically, FIGS. 27 and 28 are related to the interfacerequirements, FIGS. 30 through 33 detail the telecommunicationssubsystems 12 and FIGS. 34 through 40 detail audio multimedia circuitry18.

There are 2 telecommunications functions which are included as anintegral part of the audio multimedia implementation because of theirclose inter-relationship. The first telecommunications interface is aSmall Computer Systems Interface, SCSI 13. This is a general purposedigital interface widely endorsed in the computer industry and mostcommonly used to support mass storage device. In this particularapplication the mass storage device of choice is a Compact Disc player,CD 28. The SCSI interface 13 provides operational control of the CDplayer.

This Compact Disk device is specially adapted to handle both digitaldata media (disks) as well as digital audio media, thereby allowing itto function as a data retrieval device as well as an audio reproducingdevice. Because this device can handle digital data media, it is alsoreferred to as a Compact Disk Read Only Memory device or CD-ROM. It isbecause of its audio reproduction capabilities that this device is anintegral part of the audio multimedia implementation.

The second telecommunications function related to the audio multimediaimplementation is a Musical Instrument Digital Interface, MIDI 30. MIDIis a well established industry standard digital interface for connectingmusical instruments and controllers. The data communicated via MIDIcontrols the generation of sounds, i.e. selecting the sound's attributessuch as timbre, pitch and envelope and then turning the sound(s)on/off/up/down. While this information itself is not audio it can beused to create audio in the multimedia circuitry with the aid ofsoftware to convert the MIDI information into the appropriateprogramming of the sound synthesizer 33 to create an electronic musicalinstrument.

FIG. 26 shows the clock generation for the A/D-D/A converter. The mastersample rate clock of 44.1 KHz can be generated either by an oscillator350 or via a PAL 351 which divides a 14.318 MHz clock which is availablefrom host interface 300. PAL 351 divides the 14.318 MHz by 325 to yield44.056 KHz.

FIG. 27 also depicts a group of buffers for address 312, control 313 anddata 311. These buffers provide electrical isolation between hostinterface 300 and the rest of the multimedia circuitry 18. PAL 303provides some address decoding for functions of the multimedia circuitryas well as controls the enabling of the output of data buffer 311.

FIG. 28 shows the host computer interface 300. This interface is fullyIBM PC-AT compatible.

FIG. 29 provides a detailed schematic drawing of sound synthesizer 33.The sound generator interface 33 of FIG. 29 uses a Yamaha YM3812 in thepreferred embodiment. The FM sound generator chip is programmable byinternal registers. Three modes of sound generation are possible:simultaneous voicing of 9 sounds is one mode, a second mode provides 6melody sounds in conjunction with 5 rhythm sounds (the 5 rhythm soundsare bass drum, snare drum, tom-tom, top cymbal and high hat symbol); andthirdly there is a speech synthesis mode. There is also a built-invibrato oscillator with an amplitude modulation oscillator. Softwarecompatibility for commercially available sound generator hardwarerequires I/O addresses of 0388 hex and 0389 hex. The Yamaha applicationmanual for the YM3812 provides register descriptions and additionalinformation sufficient for the purposes of the present invention.

The internal parts of sound synthesizer 33 are functionally divided intonine blocks to perform various functions. The blocks include the (1)register array; (2) phase generator; (3) envelope generator; (4)operator; (5) accumulator; (6) vibrator oscillator/amplitude modulationoscillator; (7) timers; (8) data bus controller; and (9) timingcontroller.

The register array controls sound synthesizer 33. The phase generatorreceives and accumulates phases from the register array, therebycalculating a phase at each time step. The envelope generator generatesan envelope and modulation index for each sound. The envelope generatoralso receives instructions for such items as slope and offset from theregister array to generate an envelope. The operator receives phaseinformation from the phase generator and envelope information from theenvelope generator, and calculates the period and magnitude ofoperation. The accumulator is used to accumulate each sound at eachsampling time in order to convert data to match the D/A converter. Lowfrequency oscillators control vibrato and amplitude modulation. Theoscillation frequency is 6.4 Hz for vibrato and 3.7 Hz for amplitudemodulation. Two types of timers are provided for general purpose longand short periods. Data bus control and timing control are alsoprovided.

FIGS. 30 through 32 provide detailed schematic drawings for the SCSIinterface 310 of the present invention. FIG. 30 shows the SCSIcontroller 310, FIG. 31 shows the SCSI bus interface 317, and FIG. 32the BIOS ROM 329 and option switches 331 for the preferred embodiment.

The SCSI interface 310 of FIG. 30 is a single chip controller and isranked as a second generation SCSI chip. The hardware provides a 128byte FIFO for data bus and an 8 byte FIFO for SCSI bus transfers. TheSCSI interface 310 supports both synchronous and synchronous bustransfers. Automatic selection and reselection of SCSI sequences areperformed by the hardware to reduce the need for host processorintervention. The SCSI controller can support data transfer rates of upto 4 megabytes/second. The SCSI interface 310 will support internal andexternal devices.

SCSI interface 310 is a single-chip adapter for host computer 24 thatprovides low-cost connectivity to multiple SCSI peripherals. SCSIinterface 310 supports 8-bit DMA or 16-PIO transfers with the hostcomputer 24. Supporting up to eight simultaneous I/O tasks the SCSIinterface of the preferred embodiment is part number AIC-6260manufactured by Adaptec, Inc.

Adaptec provides a software DOS manager and several drivers for SCSIdevices. The CD-ROMS, hard disks and tape drives are currently supportedby Adaptec with software drivers. The Adaptec reference guide for theAIC-6260 preferred embodiment provides register descriptions appropriatefor the purposes of the present invention.

FIG. 33 illustrates the detailed schematic for MIDI interface 30 of thepreferred embodiment. MIDI 30 is comprised of a single channelsynchronous communications element (ACE) capable of buffering up to 16bytes of data for transmission and up to 128 bytes of data on reception.MIDI 30 contains an integral FIFO threshold trigger level that isprogrammable to 1, 4, 8, or 14 bytes. Internal registers allowprogramming of various types of interrupts, modem controls, characterformats, and data rate. The MIDI 30 is a software oriented device usinga three-state, 8-bit, bi-directional data bus. In the preferredembodiment, MIDI is the Yamaha 3802.

The MIDI interface 30 of FIG. 33 is very similar to a serial port. Theonly differences are a fixed clock rate of 31,250 baud (which is derivedfrom the 14.318 MHz bus signal oscillator), and the electricalinterface, an optically isolated 5 milliamp current loop. Threeconnections are provided, including MIDI in, MIDI out and MIDI passthrough. There is a single 6-pin mini-din connector on the back of themultimedia board. A “Y” cable will be necessary to make the actual MIDIhardware compatible connections. This “Y” cable is IBM® PS1® compatible.The MIDI interface is implemented with a Yamaha YM3802 chip. The Yamahachip is a specific MIDI interface device with integral FIFO, (128 bytecapacity input and 16 byte capacity output), a 14 bit counter/timer andseveral other MIDI specific functions. The Yamaha application manual forthe YM3802 provides register descriptions and programming informationfor MIDI interface 30. Various software drivers are available forintegration of the YM3802 into the multimedia environment.

FIG. 34 shows the detailed schematic diagram of the clock generationcircuit 343 necessary for the proper operation of MIDI interface 30 andprogrammable timer 341. Connections to other portions of audiomultimedia circuit are as shown in FIG. 34.

FIG. 34 shows 82C54 programmable interval timer circuit 341, which isconnected to the inputs of the sample rate selector multiplexer. If therate selection is set at 00, then timer 1 generates the sample rate andTimer 0 generates the filter clock for the converter. The timers shouldbe set to run in mode 3, square wave generator. The input clock is 10MHz. This will yield a wide range of possible sample frequencies. Thereis a caution in that 10 MHz does not perfectly divide to the desirable44.1 kHz signal, but the error is only 0.1% (i.e., 10 MHz/227=44.0528kHz). Timer 0 should always be programmed to produce an output which isnot more than 25 times the frequency of timer 1. A value of 20 times isrecommended. The timers are programmed according to the standardspecification and I/O addresses are assigned 38C timer 0, 38D timer 1,38E timer 2, and 38F timer control register. Alternate addresses are notselectable.

FIGS. 35 through 37 show the detailed schematic of A/D-D/A converter 32and DMA state machine 315. FIG. 35 shows the A/D-D/A converter 32detailed schematic, FIG. 36 shows the digital-to-analog output filterfor D/A-A/D converter 32. FIG. 37 shows the converter controller or DMAstate machine 315 that controls converter 32.

FIG. 35 illustrates A/D-D/A converter 32 that consists of an 8-bit A/Dconverter and a D/A converter in a single chip. The interface supportsdirect programmed I/O and DMA access. While programmed I/O is simple tohandle, DMA provides for a more consistent sample rate with resultingbetter fidelity. It is not possible to support simultaneous DMA of bothA/D and D/A. If concurrent operation is required, it can be achieved byrunning one direction DMA and the other programmed I/O. Two I/O portsare provided, I/O port 332 controls the DMA parameters and returns thestatus. The second allows direct access to the digital data for theconverters 32.

The following are the definitions for the control port 322 bits for DMAcontrol of A/D-D/A converter 32:

Bit 7 is the enable DMA analog-to-digital converter. When set, this bitstarts the A/D converter sampling. The sample rate is selected by thesetting of bits 3 and 4 and the programming of 8254 341 timers 0 and 1.When a conversion is complete, a DRQ will be sent to the host. This willresult in the data being transferred to the host.

Bit 6 enables the DMA digital-to-analog conversion. When set, this bitinitiates a DRQ to the host for transmission of the first byte of datafor the D/A converter. When the converter has accepted this byte, a newone will be requested at the appropriate time to support the selecteddata rate.

Bit 5 is a continuous mode bit. When reset, the active DMA device willterminate activity when the terminal count is reached. Terminal count isreached when the host DMA controller detects and end of the currentbuffer. When the terminal count is reached, an interrupt will begenerated. When set, an interrupt will be generated at the terminalcount, but activity will continue. This mode is intended to complementthe auto-initialize mode on the DMA controller. It is the responsibilityof the driver to allow buffer wraparound at interrupt or be able toreconfigure the DMA controller for a new buffer before the next DMAtransfer occurs. Bits 4 and 3 control a multiplexer which selects thesample and filter clocks. These two bits define the converter samplerate as follows: −4−3 defines sample rate set by timer 0 and 1; −4+311.025 kHz; +4−3 22.05 kHz; and +4+3 44.100 kHz.

Bits 2, 1 and 0 are not associated with the converters, but are definedas follows:

Bit 2: TIMER 2 COUNT ENABLE. This bit is connected to the GATE 2 inputof the 82C54. When set to 1 it allows the timer to run, when set to 0 itdisallows the timer to count. For further functions refer to the 82C54programming specifications.

Bit 1: TIMER 2 INTERRUPT ENABLE. This bit when set to 1 allows timer 2to generate an interrupt whose status is available in the main statusregister bit 5. When this bit is 0, timer 2 interrupts are disabled andreset, and status bit 5 is reset.

Bit 0 is the audio amplifier enable bit. This bit enables the poweramplifier for the speakers. When set to a 1, the amplifiers are enabled.When set to a 0, the amplifiers are muted. When the multimedia board isfirst powered up, the amplifiers are disabled to prevent uncontrolledoutput from occurring.

All bits in this register are reset upon power up.

The preferred embodiment of the present invention uses an Analog DevicesAD7569 8-bit analog I/O system as A/D-D/A converter 32. A/D-D/Aconverter 32, as such, contains a high speed successive approximationADC with 2 μsec conversion time, a track/hold amplifier with 200 kHzbandwidth, a DAC and output buffer amplifier with 1 μsec. settling time.A temperature-compensated 1.25 V bandgap reference provides a precisionreference voltage for the ADC and the DAC.

Due to the Nyquist theorem of aliasing of digitally sampled signals itis necessary to limit the band pass of signals being sampled to lessthan ½ the sample rate. In order to provide maximum flexibility ofsample rates, i.e. any integral division of 10 MHz covering the rangefrom 1 KHZ through 48 KHz, a flexible bandpass filter is required. Themost expedient approach is to utilize a clocked switched capacitorfilter system.

In the preferred embodiment a pair of MF4 devices are used, 346 and 348,one each for the ADC and DAC channels. These devices in conjunction withan associated op amp, 347 and 349, provide effective 5 pole low passButterworth filters to limit upper bandwidth. The MF4 filters 346 and348 are 4th order Butterworth filters and provide 3 db rolloff at afrequency which is approximately {fraction (1/50)} th of their inputclock. This input clock is selected through multiplexer 350, FIG. 3B.The source of these filter clocks can be either oscillator Y2 350 or PAL351 on FIG. 27, or Programmable Interval Timer 341 of FIG. 34, viamultiplexer 350, FIG. 38.

Selecting a filter clock frequency of 25 times the sample clockfrequency will result in a rolloff at ½ the sample rate, I.E.Fcutoff=Fclock/50, for Fc=Fsample-rate/2 then Fsample-rate/2=Fclock/50or Fclk=25Fsample-rate. When using the interval timer 341 a value of 20×is recommended to provide addition margin without unduly sacrificingbandwidth.

FIG. 35 also illustrates the microphone interface 77. This consists ofIC 333 and associated components. IC 333 is an amplifier for themicrophone input 76. In the preferred embodiment this device is an NE575compander. It is configured as an Automatic Loudness Control such thatuser adjustment of volume level is obviated without regard of theproximity of the microphone to the input sound source. Thisconfiguration limits the volume level that is input to the A/D converter32, minimizing the amount of clipping that would occur should the inputexceed the dynamic range of the converter 32.

FIG. 36 shows main status register 342 which provides status informationfor the various functions of the audio multimedia circuitry 18. Inparticular, the main status register 342 details which device isrequesting interrupt service. This is because some of the devices sharea common hardware interrupt. Main status register 342 is a read onlyregister.

Referring to main status register 342, the following are the bitdefinitions in the preferred embodiment:

Bits 7 and 6 are undefined.

Bit 5 is a timer interrupt that reflects the output of the 8254 timer 2341 which is undedicated. When set, to a 0 the timer has an interrupt.

Bit 4 is for the remote control data available interrupt. This bit, when0, indicates that the remote control data buffer is full. This bit isreset by reading the data port on remote control circuit 50. If noremote control circuit is present, this bit is always false.

Bit 3 is a synthesizer interrupt that the sound synthesizer, YM3811, haspending if the bit is 0. Bit 2 is the audio serial bus ready input, whenhigh, this bit indicates that the serial bus which controls the mixerand volume control is available. When low, the serial bus is busy andmust not be accessed because this will corrupt the previously loadedcommand.

Bit 1 is a DMA interrupt. When the DMA channel has reached terminalcount, this bit is set to 0. This bit can be reset (to clear theinterrupt) by either disabling the active channel or, in continuousmode, by resetting and restoring the continuous mode bit. Resetting theactive channel in continuous mode will terminate the channel and theinterrupt, whereas toggling the mode bit will reset the interrupt whileallowing DMA to continue. Finally, bit 0 is the MIDI port interrupt bit.When this bit is 0, the MIDI controller, YM3802. in the preferredembodiment, has an interrupt pending. The interrupt vector is readableat I/O port 221 h. This bit is reset by reading the UART's data port.

An undedicated timer interrupt is provided from the output of an 82C54,341 timer 2. This timer runs at 10 MHz and may be programmed in anymanner as may be required. Status of the interrupt is in the main statusregister 342 bit 5. The timer is accessible as I/O addresses 38 e and 38f.

FIG. 36 also shows the MF4 filter 348 and op amp 349 for the D/Aconverter. The audio power amplifiers 326 are shown along with a poweron muting circuit 327. This circuit prevents unintentional noise frombeing passed to the speakers during the interval between when power isfirst applied to the circuit and the time that intentional output isdesired. This circuit is controlled by DMA Control Register 322 bit 0.

Finally, FIG. 36 shows the voltage regulators 325 that provide isolatedpower to the low level audio circuits. These regulators minimize noisefrom host computer 24 being injected into the audio paths.

FIG. 37 illustrates the detailed schematic of DMA state machine 315. Theanalog-to-digital state machine is simple; analog-to-digital conversionsare begun at the falling edge of the digital-to-analog conversion clock,to keep them synchronous. The conversion complete status signal ADC_DONEfrom the converter is used to generate a DMA transfer request to hostcomputer 24. When the data is transferred the request is reset.Sufficient time should exist between completion of an analog-to-digitalconversion and the next falling edge of the digital-to-analog conversionclock for a DMA read to occur without danger of overrun.

The digital-to-analog sequence requires prefetching a byte prior to thenext rising edge of the digital-to-analog conversion clock whereupon itis loaded into the converter. A DRQ is immediately started when theanalog-to-digital converter is enabled. Once the byte is received, it istemporarily latched in a register until the next rising edge of thedigital-to-analog converter clock. It is then loaded into thedigital-to-analog converter and a new byte is requested. Again, use ofthe digital-to-analog converter clock keeps the data flow constant.

Interrupts are generated whenever a terminal count is reached. In“normal” mode, the terminal count also terminates the DMA state machineand no more transfers will occur. Interrupt can be reset by disablingthe device that was active. In “continuous” mode, an interrupt occurs atthe terminal count, but transfers continue by wrapping around to thebeginning of the buffer. Interrupt can be reset by toggling theContinuous control bit in DMA control port 322 off, then on,sequentially. This will not affect the operation of the tranwfermachines.

Due to complexity, simultaneous DMA operation of both thedigital-to-analog converter and analog-to-digital converter isprohibited. It is possible however, to do both DMA analog-to-digitalconversion operations and programmed I/O operations to thedigital-to-analog converter, but stability of the digital-to-analogconversion rate is less accurate. Attempting to do DMA digital-to-analogconversions and simultaneously programmed I/O to the analog-to-digitalconverter will result in intermittent erroneous data being returned dueto the fact that there is no way to block the digital-to-analogconverter load if it occurs during a read. Since there is only bus, itwill be directed towards the converter and a read will return null data.

DMA State Machine 315 consists of PALs 361, 362 and 365, synchronizingregister 364 and data register 363. DMA Control Register 322 enables theDMA State Machine and controls its operating parameters. Buffer 366provides readback capability of Control register 322.

PAL 365 provides address and command decoding for the DMA State Machine315. PAL 361 controls the generation of DMA data transfer requests, DMAgenerated interrupts and A/D conversion starts. PAL 362 controls theactual data transfer during either DMA or programmed I/O. It manages thedirection and latch controls of buffer 363. Synchronizing register 364prevents metastability problems from occurring in the DMA State Machinedue to the different operating clocks between the DMA State Machine 315and host computer 24.

FIG. 38 shows the serial bus controller 316 of the preferred embodimentof the present invention. Serial bus controller 316 controls mixer 70and volume/tone controller 319. Serial bus controller 316 is a pair ofwrite only registers that accept the 16 bit command for the devices asdefined by Toshiba. The registers may be loaded individually orsimultaneously. If they are loaded serially, the high register must bethe last loaded. When the high register is loaded, a sequencer isstarted which sends the data to the controllers. This takesapproximately 80 μs. In order to monitor the status of the sequencer, abusy indicator is provided in the main status register 342. When the bitis high, the bus is available for loading a new command. When low, a newcommand must not be loaded, as it will corrupt the current transmissionin progress.

Serial bus controller 316 comprises a 16-bit shift register 370 andassociated PALs 371 and 372 to generate the clock signals necessary toget control information transferred to the volume control 318 and 7:1mixer 70.

PAL 371 decodes the serial bus commands as sent by host computer 24 andcontrols loading of volume/tone/mixer information into shift register370. It also initializes sequence counter PAL 372. PAL 372 generates theclocks and strobe signals necessary to transfer the volume/tone/mixerinformation from the input to the output of shift register 370 andeventually to the Volume Control 318 and Mixer 70.

FIG. 38 shows the generation and selection of clocks necessary tooperate the DMA State Machine 315, the Serial Bus Controller 316, theA/D-D/A converter 32 and the filters 346 and 348. A 14.318181 MHz clockis received from host interface 300 and scaled by divider 373 to producea number of low frequency clocks. 7.1 MHz and 3.58 MHz are used by theDMA State Machine. 223 KHz is used by the Serial Bus Controller 316. 894KHz, 447 KHz and 223 KHz can be used by filters 346 and 348. 44.1 KHzfrom oscillator 350 is divided by flip flops 374 to provide 22.05 KHzand 11.025 KHz. These three frequencies are the preferred sample ratesfor the A/D-D/A converter 32. Selection of the converter sample rate andfilter clock is via multiplexer 352.

FIGS. 39 and 40 are schematics of audio subsection including 7:1 mixer70 and volume/tone control 318. 7:1 mixer 70 has 7 input channelsincluding: (1) stereo CD player 28 input; (2) D/A converter 32 monauralinput; (3) sound synthesizer 33 monaural input; (4) AM/FM tuner circuit48 stereo input; (5) television circuit 46 monaural input; (6) auxl 72stereo input; and (7) data/fax/voice modem circuit 44 monaural input.Outputs from 7:1 mixer 70 go directly to volume control 318. Mixer 70also includes a pair of stereo switches which are configured to providestereo to monaural conversion and selection of microphone input 76 ormixer 70 output as input for A/D converter 32. Mixer 76 allows selectingany or all inputs. Twelve levels of mixer volume are provided. Forspecific programming information, refer to the programming specificationfor the Toshiba TC9187 unit.

The detailed schematic diagram for 7:1 mixer 70 appears at FIG. 39. For7:1 mixer 70, the present invention uses a single integrated circuit,No. TC9187AF manufactured by Toshiba.

Audio mixer 70 is a digitally controlled device with 7 pairs of inputs.Although the primary application of this device is for a graphicequalizer, it is here used as a mixer since its architecture is simplyseven pairs (stereo) of independently adjustable attentuators. Bysending a control word via a serial bus interface, the various inputscan be adjusted. The control word consists of 2 bytes and is organizedas described in the following table:

Data bits 15 . . . 12 are the address of the TC9187.

Data bits 7 . . . 4 (A4 . . . A1) select the input to change as follows:

TABLE 3 A4 A3 A2 A1 1 0 0 0 FF1/FF2 input selector for A/D converter,mono/stereo selector 1 0 0 1 channel 1 (digital audio from D/Aconverter) 1 0 1 0 channel 2 (sound synthesizer) 1 0 1 1 channel 3 (CDaudio) 1 1 0 0 channel 4 (radio tuner) 1 1 0 1 channel 5 (auxiliaryinput) 1 1 1 0 channel 6 (TV sound) 1 1 1 1 channel 7 (telephone input)

Data bits 11 . . . 8 (D4 . . . D1) are used to set the step of eachvolum. These bits become the data to be used for varying, in 13 steps,the volume of the selected input. The volume settings are per thefollowing Table 4.

TABLE 4 D4 D3 D2 D1 STEP 0 1 1 0 CHANNEL FULL ON 0 1 0 1  −1 dB 0 1 0 0 −2 dB 0 0 1 1  −3 dB 0 0 1 0  −4 dB 0 0 0 1  −5 dB 0 0 0 0  −8 dB 1 1 11 −10 dB 1 1 1 0 −12 dB 1 1 0 1 −18 dB 1 1 0 0 −22 dB 1 0 1 1 −30 dB 1 01 0 CHANNEL FULLY MUTED Settings for FF1 and FF2 are: D4 D3 D2 D1 ACTIONFUNCTION x x x 1 FF1 Reset microphone is A/D input x x 1 0 FF1 Set mixeris A/D input x 1 x x FF2 Reset stereo 1 0 x x FF2 Set monaural

FF1 is a multiplexer which can switch the input to the analog-to-digitalconverter 32 between the microphone and the output of the mixer 70. Thisallows recording either voice input or any combination of other inputs.Setting FF1 will select the mixer as the input. Resetting FF1 selectsthe microphone input. FF1 is initialized to deselect the microphoneinput. FF2 selects whether the output of the mixer will be stereo ormonaural. The default condition is stereo, setting FF2 makes the outputmonaural.

FIG. 40 shows the detailed schematic diagram for the volume/tone controlcircuit 318. Volume/tone controller 319 is an integrated circuit whichallows electronic adjustment of volume, balance, treble, bass andloudness compensation of a stereo analog input. A fader adjustment isalso provided to allow relative volume adjustment between a pair ofoutputs, one connected to the power amplifiers 326 the other connectedvia buffer amps 321 to the Line/Headphone output 320.

In the preferred embodiment volume/tone controller 319 is a ToshibaTC9188F. Since this part is a passive attenuator, op amps 323 providebuffering for volume functions and bandpass shifting for tone control.Selection and control of the adjustments is under software control via aserial bus connection. Volume can be attenuated from 0 to −79 dB in 1 dBsteps. Bass and treble can be adjusted ±12 dB in 2 dB steps. One of theoutput channels can be selected to be faded from 0 to −60 dB in 16steps, or turned off completely. Loudness compensation can also beenabled or disabled.

The following table describes the organization of the control word forthe volume/control chip 319, which consists of two bytes.

Data bits 15 . . . 12 are the address of the TC9188.

Data bits 3 . . . 0 (A4 . . . A1) select the function to change asfollows:

TABLE 5 A4 A3 A2 A1 1 0 0 0 Volume Right 1 0 0 1 Volume Left 1 0 1 0Bass adjust 1 0 1 1 Treble adjust 1 1 0 0 Fader adjust

Data bits 11 through 4 appearing at D8 through D1 are used to set thestep of volume, bass, or treble. If left or right volume is selected,the data bits D8 through D1 control the volume attenuation. If volumeright is selected, D8 controls the loudness compensation for bothchannels. D8 is set to 0 to turn the loudness compensation off, D8 isset to 1 for the loudness compensation on. If volume left is selected,then D8 has no function. D7 through D5 control the volume in 10 dBincrements. Bits D4 through D1 control the volume in 1 dB steps. Thefollowing table describes the incremental volume control that bits D7through D1 provide.

TABLE 6 D7 D6 D5 STEP 0 0 0  0 dB 0 0 1 −10 dB 0 1 0 −20 dB 0 1 1 −30 dB1 0 0 −40 dB 1 0 1 −50 dB 1 1 0 −60 dB 1 1 1 −70 dB D4 D3 D2 D1 STEP 0 00 0  0 dB 0 0 0 1 −1 dB 0 0 1 0 −2 dB 0 0 1 1 −3 dB 0 1 0 0 −4 dB 0 1 01 −5 dB 0 1 1 0 −6 dB 0 1 1 1 −7 dB 1 0 0 0 −8 dB 1 0 0 1 −9 dB 1 0 1 0volume off

If bass or treble is selected, data bits D4 through D1 control thesetting. Data bits D8 through D5 are not defined. Bass and treblesettings affect both channels as the following table indicates.

TABLE 7 D4 D3 D2 D1 STEP 0 1 1 0 +12 dB 0 1 0 1 +10 dB 0 1 0 0  +8 dB 00 1 1  +6 dB 0 0 1 0  +4 dB 0 0 0 1  +2 dB 0 0 0 0  0 dB 1 1 1 1  −2 dB1 1 1 0  −4 dB 1 1 0 1  −6 dB 1 1 0 0  −8 dB 1 0 1 1 −10 dB 1 0 1 0 −12dB

If the fader is selected, data bits D4 through D1 control the fadervolume. The fader adjusts the balance between the power amplifier ofaudio multimedia circuit 18 and the head/headphone external jack. Thisallows setting the levels independently. Fader control affects bothchannels simultaneously. The fader controls attenuation only. Bit D8controls which output pair is faded. When D8 is set to 0, the lineoutput is faded, when D8 is 1, the onboard amplifier is faded. Thefollowing describes the bit sequence for fader control in volume/tonecontrol chip 319.

TABLE 8 D4 D3 D2 D1 STEP 0 0 0 0  0 dB 0 0 0 1  −2 dB 0 0 1 0  −4 dB 0 01 1  −6 dB 0 1 0 0  −8 dB 0 1 0 1 −10 dB 0 1 1 0 −12 dB 0 1 1 1 −14 dB 10 0 0 −16 dB 1 0 0 1 −18 dB 1 0 1 0 −20 dB 1 0 1 1 −26 dB 1 1 0 0 −35 dB1 1 0 1 −45 dB 1 1 1 0 −60 dB 1 1 1 1 channel off

There are three outputs available from audio multimedia circuitry 18,two of which include external connections. One is the output fromamplifier, providing 2 watt RMS/channel. Speaker impedance may be anyvalue greater than 2 ohms. Use of 4-Ω speakers is recommended becausethey can potentially deliver more volume than 8-Ω speakers. The secondoutput is a low level stereo output that can be used to drive headphonesor an external power amplifier. Volume control of this output can beindependent of the power output as provided by the TC9188. The thirdoutput is a buffered version of the input to the analog-to-digitalconverter. This output is available on one of the internal connectors.It is intended to be an input to a phone device such-as thefax/data/modem 44.

Multimedia circuitry 18 supports a number of I/O ports for control ofits functions by the host computer 24. The hex address map for theseports is as listed below where the primary address is listed first andthe alternate is listed in parentheses.

TABLE 9 I/O Address Cycle Type Register Description 0220 (0230) Readonly Main status register 0221 (0231) Read only YM3802 interrupt vector0222 (0232) Read/Write DMA control register 0224 (0234) Read/Write A/Dconverter data port 0226 (0236) Write only Audio mixer/volume controlLSB 0227 (0237) Write only Audio mixer/volume control MSB 0228 (0238)Read/Write MIDI register 0 thru 022F (023F) Read/Write MIDI register 70340 Read/Write SCSI registers thru 035E Read/Write SCSI registers 0388Read/Write FM Sound generator register 0389 Write only FM Soundgenerator register 038C Read/Write Timer 0 038D Read/Write Timer 1 038ERead/Write Timer 2 038F Read/Write Timer Control Register

There are two interrupts generated by audio multimedia circuitry 18. Oneis dedicated to SCSI controller 310. This provides compatibility withexisting drivers. The second interrupt is shared amongst the MIDIcontroller 30, sound synthesizer 33, A/D-D/A converter 32 and AM/FMtuner circuit 48. This minimizes the number of hardware resources (IRQs)required. Both of the interrupts are selectable. The options for theSCSI controller 310 are IRQ 11 and IRQ 12. IRQs 9, 10 and 15 areselectable for the second interrupt.

FIG. 41 shows component configurations for the data/fax/voice modemboard 500 that contain data/fax/voice modem circuit 44 for workstation10. Component labels correspond to identifiers of detailed schematicdrawings of FIGS. 6 through 12, above. The preferred embodiment usesdouble-sided surface mount technology and PALs for minimizing the amountof discrete logic circuits necessary for circuit logic functions. Board500 also incorporates design for electromagnetic interference isolation.

A problem that the design of board 500 overcomes is the need forshielding telephone line 22. Because it is not possible to shield thetelephone line 22, it is important to provide internal shielding in therest of the circuit that will isolate telephone line 22. By carefullyisolating the digital portions of modem circuit 44 from the analogportions, this problem is in large part solved. Ferrite beads 502suppress the harmonics as signals leave the board to stop theseemissions.

FIG. 42 shows component configurations for the television expansionboard of workstation 10 of the present invention. Component labelscorrespond to identifiers of detailed schematic drawings of FIGS. 13through 21, above. Television board 520 fits within chassis 20 alongwith other telecommunications circuitry 12 such as that ofdata/fax/voice modem circuit 44 on board 500 and includes connectionsfor video and audio input. In the preferred embodiment of the televisionboard 520, cable TV input 522 receives cable television input. VGA videoinput 524 may receive video input from a VGA controller, VCR audio input776 and speaker audio output 528, respectively, communicate audiotelevision signals between external devices and the television board520.

FIG. 43 shows component configurations for the AM/FM tuner and infraredremote control expansion board 530 of the workstation of the presentinvention. Component labels correspond to identifiers of detailedschematic drawings of FIGS. 22 through 25, above.

FIG. 44 shows component configurations for the audio multimedia board510 of the workstation of the present invention. Component labelscorrespond to identifiers of detailed schematic drawings of FIGS. 28through 40, above. Board 510 comprises analog circuitry and digitalcircuitry. The design serves to prevent cross-coupling between thedigital circuitry and the analog circuitry of the board byimplementation of separate power planes.

One significant problem that the board design overcomes is providingconnectors from each expansion board to associated boards. This isaccomplished, in part, by designing each of the expansion boards to havea full back panel associated with those components that have externalconnections. For example, audio multimedia board 510 includes microphoneinput 76, aux 172, speaker output 328, and audio line out 320. Audiomultimedia board 510 also provides MIDI in/out terminal 314. Theconnections of expansion boards for the workstation are designed toallow the maximum amount of connectivity with the minimal amount ofconsumed space at the rear of the workstation chassis 20.

FIG. 45 shows the use of expansion bracket assembly 540 to receive thetelecommunications and multi-media circuits associated with the presentinvention. In particular, within expansion bracket assembly 540, audiomulti-media expansion board 510 and television board 520 are positionedto engage connected circuitry of expansion bracket assembly 540. On theopposite side, the preferred embodiment mounts data/fax/voice modemboard 500 beneath AM/FM tuner —infrared remote control board 530.

FIG. 46 illustrates the further connection of expansion bracket assembly540 into chassis 20 of the preferred embodiment. According to FIG. 46,expansion bracket assembly 540 is comprised of riser board 542 and cardedge guide 544. Expansion bracket assembly 540 is described in moredetail in U.S. Pat. No. 4,979,075 by J. Murphy and entitled “ExpansionCard Assembly” issued on Dec. 18, 1990. With the expansion boardsdescribed in FIG. 45, expansion bracket assembly 540 engages and mountsabove mother board assembly 546. Mother board assembly 546 mounts withinchassis 20 above floppy drive bracket 548 and hard drive bracket 554within chassis base 556. System bezel 558 mounts to the front of chassisbase 556. Battery pack 560 and power supply 562 fit comfortably withinchassis 20.

FIG. 47 shows an isometric view of fully assembled chassis 20 of thepresent invention. Across system bezel 558 appears 5-¼″ floppy drive 38to receive diskettes. Along the right-hand front side of system bezel558 appears CD-ROM drive 28. Also beside CD-ROM drive 28 appearsinfrared photodiode 466 to receive input signals from remote controller52 (See FIG. 1).

FIG. 48 shows the reverse panel of chassis 20 to illustrate the compactinput output connections associated with the telecommunications inmultimedia circuits of the present invention. Across the top of FIG. 48appear rear brackets of data/fax/voice modem board 500, AM/FM tuner—IRremote control board 530, audio multimedia board 510, and televisionboard 520. For data/fax/voice modem board 500, connections include phoneline input 564, connection 566 for a desk phone, and connection 127 toan external speaker.

For AM/FM tuner—infrared remote control board 530, connections includeAM/FM antenna input 296, external speaker output 278, line level audiooutput 276, and external infrared receiver input 294. Connections foraudio multimedia board 510 include audio output 328 to speakerconnections, line output 320 to headphones or other audio loads,auxiliary audio input 72, microphone input connection 76, andMIDI-in-out-through connection 314. Television board 520 connectionsinclude TV cable or VHF/UHF connection 522, input 524 from computervideo output of a VGA card, video output connector 592 to connect to VGAmonitor 26 (See FIG. 1), audio/video input connector 776 from a cameraor VCR, and audio output 528 (either line or amplified).

FIG. 48 also illustrates how expansion bracket assembly 540 fits at therear panel of chassis 20. Other connections at the rear of chassis 20include AC outlet 598 and AC power input 600 for power connections topower supply 562. Mouse connection 602 provides access for a pointingdevice. SCSI port 604 provides connection for external SCSI devices.Game port 606 permits the connection of a joy stick for various computergames. Keyboard connection 608 allows connection of standard keyboard.Other port connections include parallel port 610 and serial one port612, and serial two port 614. Mother board VGA output connector 616permits connection of a VGA monitor to mother board 546 (FIG. 46).

In order to operate workstation 10 of the present invention, it isdesirable to use a multimedia graphical user interface software system.The preferred embodiment of the present invention uses the MultimediaWindows software system to support the telecommunications and audiomultimedia circuitry. FIG. 49 illustrates the hierarchical structure ofapplication programs for workstation 10 of the present invention for agiven application 620. The multimedia graphical user interface softwareused in conjunction with the present invention has a number ofcharacteristics that are different from usual graphical user interfacesoftware systems. The following paragraphs describe the differencesbetween the multimedia graphical user interface software and most othergraphical user interface software systems. After describing thedifferences, the following paragraphs describe the driver types used inthe workstation 10 of the present invention.

The first difference for this graphical user interface, in particularthe multimedia windows system is that this system supports audio inputsand outputs as well as digitally sampled sound. Audio input can be usedfor creating sampled sound for voice annotations as well as basicmultimedia productions. The sampled audio can also be played back fromdisk, for example, as in a compact disk. Additionally, the multimediagraphical user interface software supports external media devices suchas CD-ROMs and video disk players. High capacity media devices can becontrolled from within the multimedia graphical user interface softwareto provide high quality audio or video playback without havingtremendous storage requirements. Yet another difference in themultimedia graphical user interface software is that the softwaresupports MIDI instrument emulation using FM synthesis and a standardMIDI patch table. This provides the ability for a multimedia author toadd a musical score to a production in a device independent fashionwithout incurring the high data storage cost of sampled sound.

Another difference in the multimedia graphical user interface- softwareis its support for MIDI input and output. This allows MIDI scores to becomposed and played back on more sophisticated sound equipment than theconventional “PC MIDI” instrument emulator.

The multimedia graphical user interface software also provides enhancedvideo drivers. Device independent bit maps (DIBs) are in software toallow an application access to a high performance mechanism thatdirectly manipulates a bit map image of a region of the screen. Thisallows frame-based animation of a portion of the screen. Finally, themultimedia graphical user interface software used in the presentinvention provides enhanced timer services. This makes possiblesynchronization of audio and video events.

Driver types used in the workstation 10 of the present inventionacknowledge the fact that each addition that requires a new piece ofhardware also requires a driver to interface the graphical userinterface system. In the present invention, there are essentially fourtypes of drivers, including DOS/TSR drivers, normal graphical userinterface drivers, multimedia drivers, and system drivers.

In the workstation 10 of the present invention, a DOS/TSR driver 640will be used to implement communication functions for the data/fax/voicemodem circuit 44. For these applications, the GUI software 636 and GUIdriver 638 as well as DOS/TSR driver 640 of FIG. 49 illustrate thisrelationship. The multimedia graphical user interface software of thepresent invention includes two major modules that contain most of themultimedia functions. As FIG. 49 indicates, control for external devicesis provided by the media control interface 622 and by the multimediasystem dynamic link library (DLL) 628. The multimedia system DLL 628provides direct access to all of the individual multimedia devicesthrough multimedia drivers 630.

Although the media control interface 622 is a logically higher levelapplications programming interface (API) as shown in FIG. 49, itphysically resides in multimedia system DLL 628. The multimedia drivers630 are typically provided by each manufacturer for their own uniquehardware. The graphical user interface used in the present inventiondefines entry points and messages between multimedia system DLL 628 andmultimedia driver 630, so each manufacturer only has to provide thedrivers to make its hardware work with the present invention. This issimilar to the way in which conventional video drivers are interfaced tonormal graphical user interface software. In short, multimedia systemDLL 628 provides a consistent interface for application programs andmultimedia drivers 630 do the actual communication with the hardware.

The audio multimedia circuit provides sampled sound in, sampled soundout, MIDI in, MIDI out, and MIDI instrument functions for the presentinvention. System drivers 626 will use the multimedia graphical userinterface specified interfaces for these functions. A new API for thespecial features unique to the present invention are defined in systemsoftware DLL 624. System software dynamic link library 624 is analogousto multimedia system DLL 628 in the sense that it will define a standardinterface for applications. This also allows authoring tools to connectto the enhanced workstation multimedia functions. System software DLLuses system driver 626 to talk directly to various hardware componentswithin the present invention.

A special case of system drivers 626 is the CD-ROM 28 driver set. TheCD-ROM 28 driver set comprises the MSCDEX (Microsoft CD-ROM extension)632 and hardware specific CD-ROM driver 634. CD-ROM driver 634 specifiedto drive while MSCDEX 632 provides DOS file level access to the driver.MSCDEX 632 essentially lets the DOS file system access the CD-ROM 28 asanother drive on the system. In this manner, CD-ROM 28 can be used as adata storage device. MSCDEX 632 also provides access to audio functionsof CD-ROM 28 such as playing an audio compact disk. MSCDEX 632 isanalogous to the multimedia system DLL 628 in the sense that MSCDEX 632provides a standard interface and the hardware specific driver, CD-ROM634, communicates directly with CD-ROM 28. The major difference betweengraphical user interface drivers 638 and CD-ROM driver 634 is thatCD-ROM 634 works from DOS as well as within the graphical user interfacesoftware.

Although the invention has been described with reference to the abovespecified embodiments, this description is not meant to be construed ina limiting sense. Various modifications of the disclosed embodiment, aswell as alternative embodiments of the invention will become apparent topersons skilled in the art upon reference to the above description. Itis therefore contemplated that the appended claims will cover suchmodifications that fall within the true scope of the invention.

What is claimed is:
 1. A multimedia personal computer, comprising: apersonal computer, said personal computer comprising a personal computerchassis and a personal computer monitor; telecommunications circuitryintegrated with said personal computer, said telecommunicationscircuitry comprising: a data/fax/voice modem associated with saidpersonal computer and allowing communication of voice, fax and datainformation over a telephone line: a television circuit associated withsaid personal computer for receiving a plurality of television signalsand directing said signals to said personal computer monitor for saidpersonal computer monitor to display; and control circuitry associatedwith said television circuit and said personal computer for controllingthe operation of said television circuit through said personal computer;multimedia circuitry integrated with said personal computer, saidmultimedia circuitry allowing playing of audio on a speaker anddisplaying digital multimedia including text, image and video on saidpersonal computer monitor; said multimedia circuitry comprising: acompact disc read-only memory device associated with said personalcomputer; and an audio multimedia circuit associated with said personalcomputer and said television circuit for receiving and processing audiomultimedia data from said television circuit and communicating saidaudio multimedia data to said personal computer, said audio multimediacircuit comprising an analog mixing circuit for mixing a plurality ofanalog audio signals, and an analog-to-digital/digital-to-analogconverter in association with said analog mixing circuit for generatinga plurality of analog output signals and directing said analog outputsignals to said analog mixing circuit, saidanalog-to-digital/digital-to-analog converter further associated withsaid analog mixing circuit for receiving a plurality of analog audiosignals to generate a plurality of digital output signals; and softwareapplications integrated with said personal computer, said softwareapplications providing interfaces to said telecommunications circuitryand said multimedia circuitry.
 2. The television of claim 1, furthercomprising digital sound mixing circuitry and digital synthesizing soundcircuitry for directing digital signals into saidanalog-to-digital/digital-to-analog converter and from saidanalog-to-digital/digital-to-analog circuit to said analog mixingcircuit.
 3. The television of claim 1, wherein said audio multimediacircuit further comprises a compact disk read only memory device inassociation with said analog mixing circuit for transmitting to saidanalog mixing circuit a plurality of prerecorded audio signals.
 4. Thetelevision of claim 1, wherein said audio multimedia circuit furthercomprises a speaker circuit for directing analog signals to a speaker,said speaker circuit comprising selectable input circuitry forcontrollably selecting between analog microphone and analog mixer outputto digital recorder.
 5. The television of claim 1, wherein said audiomultimedia circuit further comprises a SCSI interface for interfacing aplurality of external devices with said audio multimedia circuit.
 6. Thetelevision of claim 1, wherein said audio multimedia circuit furthercomprises a musical instrument device interface for interfacing aplurality of musical devices with said analog mixing circuit.
 7. Thetelevision of claim 1, wherein said audio multimedia circuit furthercomprises a sound generator for interfacing said analog mixing circuitryand generating a plurality of predetermined types of sounds.
 8. Thetelevision of claim 1, wherein said audio multimedia circuit furthercomprises a serial line level output for generating a plurality ofstereo signals to an external stereo signal connection.
 9. Amultipurpose computerized television for generating a plurality of videoimages in association with a personal computer, comprising: a personalcomputer, said personal computer comprising a personal computer chassisand a monitor; a television circuit associated with said personalcomputer for receiving a plurality of television signals and directingsaid signals to said monitor for said monitor to display, said monitorcomprising a video graphics array monitor and said television circuitfurther comprises circuitry for associating said television circuit withvideo graphics array monitor circuitry; an audio multimedia circuitassociated with said personal computer and said television circuit forreceiving and processing audio multimedia data from said televisioncircuit and communicating said audio multimedia data to said personalcomputer, said audio multimedia circuit comprising an analog mixingcircuit for mixing a plurality of analog audio signals, and ananalog-to-digital/digital-to-analog converter in association with saidanalog mixing circuit for generating a plurality of analog outputsignals and directing said analog output signals to said analog mixingcircuit, said analog-to-digital/digital-to-analog converter furtherassociated with said analog mixing circuit for receiving a plurality ofanalog audio signals to generate a plurality of digital output signals;and control circuitry associated with said television circuit and saidpersonal computer for controlling the operation of said televisioncircuit through said personal computer, said control circuitrycomprising a remote control circuit for remotely and independentlycontrolling said television circuit and said personal computer.
 10. Amethod for generating a plurality of video television images inassociation with a personal computer for improved control andmanipulation of television signals, comprising the steps of: associatinga personal computer with a television circuit and a control circuit,said personal computer comprising a personal computer chassis and amonitor; receiving a plurality of television signals and directing saidsignals to said monitor for said monitor to display; controlling theoperation of said television circuit through said personal computer;receiving and processing audio multimedia data from said televisioncircuit and communicating said audio multimedia data to said personalcomputer; and mixing a plurality of analog audio signals using an analogmixing circuit, and generating a plurality of analog output signals anddirecting said analog output signals to said analog mixing circuit usingan analog-to-digital/digital-to-analog converter in association withsaid analog mixing circuit, and further associating saidanalog-to-digital/digital-to-analog converter with said analog mixingcircuit for receiving a plurality of analog audio signals to generate aplurality of digital output signals.
 11. The method of claim 10, furthercomprising the steps of directing digital signals into saidanalog-to-digital/digital-to-analog converter and from saidanalog-to-digital/digital-to-analog circuit to said analog mixingcircuit.
 12. The method of claim 10, further comprising the step oftransmitting to said analog mixing circuit a plurality of prerecordedaudio signals using a compact disk read only memory device inassociation with said analog mixing circuit.
 13. The method of claim 10,further comprising the step of directing analog signals to a speaker,said speaker circuit comprising selectable input circuitry forcontrollably selecting between analog microphone and analog mixer outputto digital recorder.
 14. The method of claim 10, further comprising thestep of interfacing a plurality of external devices with said audiomultimedia circuit using a SCSI interface.
 15. The method of claim 10,further comprising the step of interfacing a plurality of musicaldevices with said analog mixing circuit.
 16. The method of claim 10,further comprising the step of interfacing said analog mixing circuitwith a sound generator and generating a plurality of predetermined typesof sounds.
 17. The method of claim 10, further comprising the step ofgenerating a plurality of stereo signals to an external stereo systemconnection.